diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2016-05-27 01:34:59 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-27 11:24:17 -0400 |
commit | 4851d71e92d3c2c9fa2991a6a50d0eded7cac81b (patch) | |
tree | 0c10fa4e4d8ee6d423d7ca6e7b87492e122982e5 /drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |
parent | ed32288ee8a0664ebe6cd42a290deb0e07ebe356 (diff) |
gpu: nvgpu: align DMA base in chip HAL method
align DMA base in chip HAL method instead
in generic method.
Bug N/A
Change-Id: I47a250380e083f393677b65c13d0c2c894214ca7
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1154909
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 64828a3f..51ffc552 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -960,13 +960,13 @@ static void pg_cmd_eng_buf_load_set_buf_size_v1(struct pmu_pg_cmd *pg, | |||
960 | static void pg_cmd_eng_buf_load_set_dma_base_v0(struct pmu_pg_cmd *pg, | 960 | static void pg_cmd_eng_buf_load_set_dma_base_v0(struct pmu_pg_cmd *pg, |
961 | u32 value) | 961 | u32 value) |
962 | { | 962 | { |
963 | pg->eng_buf_load_v0.dma_base = value; | 963 | pg->eng_buf_load_v0.dma_base = (value >> 8); |
964 | } | 964 | } |
965 | static void pg_cmd_eng_buf_load_set_dma_base_v1(struct pmu_pg_cmd *pg, | 965 | static void pg_cmd_eng_buf_load_set_dma_base_v1(struct pmu_pg_cmd *pg, |
966 | u32 value) | 966 | u32 value) |
967 | { | 967 | { |
968 | pg->eng_buf_load_v1.dma_desc.dma_addr.lo |= u64_lo32(value << 8); | 968 | pg->eng_buf_load_v1.dma_desc.dma_addr.lo |= u64_lo32(value); |
969 | pg->eng_buf_load_v1.dma_desc.dma_addr.hi |= u64_hi32(value << 8); | 969 | pg->eng_buf_load_v1.dma_desc.dma_addr.hi |= u64_hi32(value); |
970 | } | 970 | } |
971 | 971 | ||
972 | static void pg_cmd_eng_buf_load_set_dma_offset_v0(struct pmu_pg_cmd *pg, | 972 | static void pg_cmd_eng_buf_load_set_dma_offset_v0(struct pmu_pg_cmd *pg, |
@@ -2672,7 +2672,7 @@ int gk20a_init_pmu_bind_fecs(struct gk20a *g) | |||
2672 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size(&cmd.cmd.pg, | 2672 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size(&cmd.cmd.pg, |
2673 | pmu->pg_buf.size); | 2673 | pmu->pg_buf.size); |
2674 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base(&cmd.cmd.pg, | 2674 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base(&cmd.cmd.pg, |
2675 | u64_lo32(pmu->pg_buf.gpu_va >> 8)); | 2675 | u64_lo32(pmu->pg_buf.gpu_va)); |
2676 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset(&cmd.cmd.pg, | 2676 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset(&cmd.cmd.pg, |
2677 | (u8)(pmu->pg_buf.gpu_va & 0xFF)); | 2677 | (u8)(pmu->pg_buf.gpu_va & 0xFF)); |
2678 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx(&cmd.cmd.pg, | 2678 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx(&cmd.cmd.pg, |
@@ -2705,7 +2705,7 @@ static void pmu_setup_hw_load_zbc(struct gk20a *g) | |||
2705 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size(&cmd.cmd.pg, | 2705 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size(&cmd.cmd.pg, |
2706 | pmu->seq_buf.size); | 2706 | pmu->seq_buf.size); |
2707 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base(&cmd.cmd.pg, | 2707 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base(&cmd.cmd.pg, |
2708 | u64_lo32(pmu->seq_buf.gpu_va >> 8)); | 2708 | u64_lo32(pmu->seq_buf.gpu_va)); |
2709 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset(&cmd.cmd.pg, | 2709 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset(&cmd.cmd.pg, |
2710 | (u8)(pmu->seq_buf.gpu_va & 0xFF)); | 2710 | (u8)(pmu->seq_buf.gpu_va & 0xFF)); |
2711 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx(&cmd.cmd.pg, | 2711 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx(&cmd.cmd.pg, |