diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-04-10 13:47:02 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-13 16:44:41 -0400 |
commit | 22426a5452ba943ac48867722fb0927baf66d4ac (patch) | |
tree | 4595c635cc920e4ba2d540a6e070b89e3037c28e /drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |
parent | a0fa2b0258dafcd7a2450ab5366a49663b1d2e89 (diff) |
gpu: nvgpu: gk20a: Use new delay APIs
Use platform agnostic delay functions instead of Linux kernel APIs.
This allows removing dependency to Linux header linux/delay.h. At the
same time remove #include lines for other unused Linux headers.
JIRA NVGPU-16
Change-Id: I46b9ccb80e0b67efb86ec85676e5a55ff835c0ec
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1460113
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 3625b679..cb9e1ba1 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -16,11 +16,9 @@ | |||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include <linux/delay.h> /* for mdelay */ | ||
20 | #include <linux/firmware.h> | 19 | #include <linux/firmware.h> |
21 | #include <linux/module.h> | 20 | #include <linux/module.h> |
22 | #include <linux/debugfs.h> | 21 | #include <linux/debugfs.h> |
23 | #include <linux/dma-mapping.h> | ||
24 | #include <linux/uaccess.h> | 22 | #include <linux/uaccess.h> |
25 | 23 | ||
26 | #include <nvgpu/nvgpu_common.h> | 24 | #include <nvgpu/nvgpu_common.h> |
@@ -2326,7 +2324,7 @@ int pmu_idle(struct pmu_gk20a *pmu) | |||
2326 | idle_stat)) | 2324 | idle_stat)) |
2327 | return -EBUSY; | 2325 | return -EBUSY; |
2328 | 2326 | ||
2329 | usleep_range(100, 200); | 2327 | nvgpu_usleep_range(100, 200); |
2330 | } while (1); | 2328 | } while (1); |
2331 | 2329 | ||
2332 | gk20a_dbg_fn("done"); | 2330 | gk20a_dbg_fn("done"); |
@@ -2424,7 +2422,7 @@ int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) | |||
2424 | gk20a_dbg_fn("done"); | 2422 | gk20a_dbg_fn("done"); |
2425 | return 0; | 2423 | return 0; |
2426 | } | 2424 | } |
2427 | udelay(PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT); | 2425 | nvgpu_udelay(PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT); |
2428 | } while (!nvgpu_timeout_expired(&timeout)); | 2426 | } while (!nvgpu_timeout_expired(&timeout)); |
2429 | 2427 | ||
2430 | g->ops.mc.disable(g, mc_enable_pwr_enabled_f()); | 2428 | g->ops.mc.disable(g, mc_enable_pwr_enabled_f()); |
@@ -2785,7 +2783,7 @@ int pmu_mutex_acquire(struct pmu_gk20a *pmu, u32 id, u32 *token) | |||
2785 | nvgpu_warn(g, | 2783 | nvgpu_warn(g, |
2786 | "fail to generate mutex token: val 0x%08x", | 2784 | "fail to generate mutex token: val 0x%08x", |
2787 | owner); | 2785 | owner); |
2788 | usleep_range(20, 40); | 2786 | nvgpu_usleep_range(20, 40); |
2789 | continue; | 2787 | continue; |
2790 | } | 2788 | } |
2791 | 2789 | ||
@@ -2812,7 +2810,7 @@ int pmu_mutex_acquire(struct pmu_gk20a *pmu, u32 id, u32 *token) | |||
2812 | pwr_pmu_mutex_id_release_value_f(owner)); | 2810 | pwr_pmu_mutex_id_release_value_f(owner)); |
2813 | gk20a_writel(g, pwr_pmu_mutex_id_release_r(), data); | 2811 | gk20a_writel(g, pwr_pmu_mutex_id_release_r(), data); |
2814 | 2812 | ||
2815 | usleep_range(20, 40); | 2813 | nvgpu_usleep_range(20, 40); |
2816 | continue; | 2814 | continue; |
2817 | } | 2815 | } |
2818 | } while (max_retry-- > 0); | 2816 | } while (max_retry-- > 0); |
@@ -3448,7 +3446,7 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g) | |||
3448 | gk20a_pmu_enable_elpg(g); | 3446 | gk20a_pmu_enable_elpg(g); |
3449 | } | 3447 | } |
3450 | 3448 | ||
3451 | udelay(50); | 3449 | nvgpu_udelay(50); |
3452 | 3450 | ||
3453 | /* Enable AELPG */ | 3451 | /* Enable AELPG */ |
3454 | if (g->aelpg_enabled) { | 3452 | if (g->aelpg_enabled) { |
@@ -4335,7 +4333,7 @@ int pmu_wait_message_cond(struct pmu_gk20a *pmu, u32 timeout_ms, | |||
4335 | if (gk20a_readl(g, pwr_falcon_irqstat_r()) & servicedpmuint) | 4333 | if (gk20a_readl(g, pwr_falcon_irqstat_r()) & servicedpmuint) |
4336 | gk20a_pmu_isr(g); | 4334 | gk20a_pmu_isr(g); |
4337 | 4335 | ||
4338 | usleep_range(delay, delay * 2); | 4336 | nvgpu_usleep_range(delay, delay * 2); |
4339 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); | 4337 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); |
4340 | } while (!nvgpu_timeout_expired(&timeout)); | 4338 | } while (!nvgpu_timeout_expired(&timeout)); |
4341 | 4339 | ||
@@ -4689,7 +4687,7 @@ static int pmu_write_cmd(struct pmu_gk20a *pmu, struct pmu_cmd *cmd, | |||
4689 | do { | 4687 | do { |
4690 | err = pmu_queue_open_write(pmu, queue, cmd->hdr.size); | 4688 | err = pmu_queue_open_write(pmu, queue, cmd->hdr.size); |
4691 | if (err == -EAGAIN && !nvgpu_timeout_expired(&timeout)) | 4689 | if (err == -EAGAIN && !nvgpu_timeout_expired(&timeout)) |
4692 | usleep_range(1000, 2000); | 4690 | nvgpu_usleep_range(1000, 2000); |
4693 | else | 4691 | else |
4694 | break; | 4692 | break; |
4695 | } while (1); | 4693 | } while (1); |