diff options
author | Srirangan <smadhavan@nvidia.com> | 2018-08-02 04:45:54 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-06 20:36:39 -0400 |
commit | 17aeea4a2ffa23fc9dbcdc84cda747fe5a025131 (patch) | |
tree | d4be52f246724fb9cb99047059073b93aeb089ce /drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |
parent | 6c9daf7626567fffc9d1ccd475865e81ae90a973 (diff) |
gpu: nvgpu: gk20a: Fix MISRA 15.6 violations
This fixes errors due to single statement loop bodies
without braces, which is part of Rule 15.6 of MISRA.
This patch covers in gpu/nvgpu/gk20a/
JIRA NVGPU-989
Change-Id: I2f422e9bc2b03229f4d2c3198613169ce5e7f3ee
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1791019
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index bf4673bf..8dbeed40 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -81,9 +81,10 @@ static void print_pmu_trace(struct nvgpu_pmu *pmu) | |||
81 | 81 | ||
82 | nvgpu_err(g, "dump PMU trace buffer"); | 82 | nvgpu_err(g, "dump PMU trace buffer"); |
83 | for (i = 0; i < GK20A_PMU_TRACE_BUFSIZE; i += 0x40) { | 83 | for (i = 0; i < GK20A_PMU_TRACE_BUFSIZE; i += 0x40) { |
84 | for (j = 0; j < 0x40; j++) | 84 | for (j = 0; j < 0x40; j++) { |
85 | if (trace1[(i / 4) + j]) | 85 | if (trace1[(i / 4) + j]) |
86 | break; | 86 | break; |
87 | } | ||
87 | if (j == 0x40) | 88 | if (j == 0x40) |
88 | break; | 89 | break; |
89 | count = scnprintf(buf, 0x40, "Index %x: ", trace1[(i / 4)]); | 90 | count = scnprintf(buf, 0x40, "Index %x: ", trace1[(i / 4)]); |
@@ -634,13 +635,15 @@ void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu) | |||
634 | struct gk20a *g = gk20a_from_pmu(pmu); | 635 | struct gk20a *g = gk20a_from_pmu(pmu); |
635 | unsigned int i; | 636 | unsigned int i; |
636 | 637 | ||
637 | for (i = 0; i < pwr_pmu_mailbox__size_1_v(); i++) | 638 | for (i = 0; i < pwr_pmu_mailbox__size_1_v(); i++) { |
638 | nvgpu_err(g, "pwr_pmu_mailbox_r(%d) : 0x%x", | 639 | nvgpu_err(g, "pwr_pmu_mailbox_r(%d) : 0x%x", |
639 | i, gk20a_readl(g, pwr_pmu_mailbox_r(i))); | 640 | i, gk20a_readl(g, pwr_pmu_mailbox_r(i))); |
641 | } | ||
640 | 642 | ||
641 | for (i = 0; i < pwr_pmu_debug__size_1_v(); i++) | 643 | for (i = 0; i < pwr_pmu_debug__size_1_v(); i++) { |
642 | nvgpu_err(g, "pwr_pmu_debug_r(%d) : 0x%x", | 644 | nvgpu_err(g, "pwr_pmu_debug_r(%d) : 0x%x", |
643 | i, gk20a_readl(g, pwr_pmu_debug_r(i))); | 645 | i, gk20a_readl(g, pwr_pmu_debug_r(i))); |
646 | } | ||
644 | 647 | ||
645 | i = gk20a_readl(g, pwr_pmu_bar0_error_status_r()); | 648 | i = gk20a_readl(g, pwr_pmu_bar0_error_status_r()); |
646 | nvgpu_err(g, "pwr_pmu_bar0_error_status_r : 0x%x", i); | 649 | nvgpu_err(g, "pwr_pmu_bar0_error_status_r : 0x%x", i); |