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authorSamuel Russell <samuelr@nvidia.com>2014-09-29 16:06:03 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:11:38 -0400
commite1c819287ca56dbff9d45f9c50a518fb08fbcc46 (patch)
treed1841fff7ddc83652e5e2e99a7fc14fac8f53e37 /drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c
parent2870a4bcecf93133141aee9f4d9007f0df22cfa8 (diff)
gpu: nvgpu: Fix gpu identification for 3demc
Modify GPU detection in 3demc-bw-ratio to use the SOC Id. Bug 1364894 Change-Id: If52e8c5153e76b29d67d28c52303b095df2e8bf0 Signed-off-by: Samuel Russell <samuelr@nvidia.com> Reviewed-on: http://git-master/r/542770 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c27
1 files changed, 15 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c
index d3dabfba..59c83686 100644
--- a/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c
+++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c
@@ -43,6 +43,7 @@
43#define TEGRA_GK20A_BW_PER_FREQ 32 43#define TEGRA_GK20A_BW_PER_FREQ 32
44#define TEGRA_GM20B_BW_PER_FREQ 64 44#define TEGRA_GM20B_BW_PER_FREQ 64
45#define TEGRA_DDR3_BW_PER_FREQ 16 45#define TEGRA_DDR3_BW_PER_FREQ 16
46#define TEGRA_DDR4_BW_PER_FREQ 16
46 47
47extern struct device tegra_vpr_dev; 48extern struct device tegra_vpr_dev;
48struct gk20a_platform t132_gk20a_tegra_platform; 49struct gk20a_platform t132_gk20a_tegra_platform;
@@ -247,24 +248,26 @@ static void gk20a_tegra_prescale(struct platform_device *pdev)
247void gk20a_tegra_calibrate_emc(struct platform_device *pdev, 248void gk20a_tegra_calibrate_emc(struct platform_device *pdev,
248 struct gk20a_emc_params *emc_params) 249 struct gk20a_emc_params *emc_params)
249{ 250{
250 struct gk20a *g = get_gk20a(pdev); 251 enum tegra_chipid cid = tegra_get_chipid();
251 long gpu_bw, emc_bw; 252 long gpu_bw, emc_bw;
252 253
253 /* Detect and store gpu bw */ 254 /* store gpu bw based on soc */
254 u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; 255 switch (cid) {
255 switch (ver) { 256 case TEGRA_CHIPID_TEGRA21:
256 case GK20A_GPUID_GK20A:
257 gpu_bw = TEGRA_GK20A_BW_PER_FREQ;
258 break;
259 case GK20A_GPUID_GM20B:
260 gpu_bw = TEGRA_GM20B_BW_PER_FREQ; 257 gpu_bw = TEGRA_GM20B_BW_PER_FREQ;
261 break; 258 break;
262 default: 259 case TEGRA_CHIPID_TEGRA12:
260 case TEGRA_CHIPID_TEGRA13:
261 gpu_bw = TEGRA_GK20A_BW_PER_FREQ;
262 break;
263 case TEGRA_CHIPID_UNKNOWN:
264 default:
263 gpu_bw = 0; 265 gpu_bw = 0;
264 break; 266 break;
265 } 267 }
266 268
267 /* TODO detect DDR3 vs DDR4 */ 269 /* TODO detect DDR type.
270 * Okay for now since DDR3 and DDR4 have the same BW ratio */
268 emc_bw = TEGRA_DDR3_BW_PER_FREQ; 271 emc_bw = TEGRA_DDR3_BW_PER_FREQ;
269 272
270 /* Calculate the bandwidth ratio of gpu_freq <-> emc_freq 273 /* Calculate the bandwidth ratio of gpu_freq <-> emc_freq