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authorAlex Waterman <alexw@nvidia.com>2017-10-25 12:41:52 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-10-27 17:45:58 -0400
commit3fdb6d2e31389db65a71cad25ba907a1306e052b (patch)
treefdca69b5b2254a9183081a707a42105115a298b4 /drivers/gpu/nvgpu/gk20a/mm_gk20a.h
parent7974ad17bb7f389e5634bde58a91304918097495 (diff)
gpu: nvgpu: Remove Linux headers from mm_gk20a.h
Delte the Linux headers and make some modifications to get rid of the minor compilation issues that resulted. - Add <linux/iommu.h> to os_linux.h - Delete #if 0 code that "flushed" a buffer in gr_gk20a.c - Delete FLUSH_CPU_DCACHE() macro - Move the cache flush definitions to <nvgpu/linux/vm.h> and include this header in sim_gk20a.c. This file will not be used by QNX so this should be fine. - Add <linux/pci_ids.h> to gp106/bios_gp106.c and gp106/mclk_gp106.c. - Move function to common/linux/dmabuf.h since it is a dmabuf related function and uses a struct device pointer as an argument. JIRA NVGPU-30 Change-Id: I11f56b98524c7fac3efa91b4686592130e5f8a46 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1585510 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/mm_gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/mm_gk20a.h20
1 files changed, 1 insertions, 19 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
index 434fc422..183d6211 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
@@ -21,14 +21,10 @@
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24
24#ifndef MM_GK20A_H 25#ifndef MM_GK20A_H
25#define MM_GK20A_H 26#define MM_GK20A_H
26 27
27#include <linux/scatterlist.h>
28#include <linux/iommu.h>
29#include <asm/dma-iommu.h>
30#include <asm/cacheflush.h>
31
32#include <nvgpu/nvgpu_mem.h> 28#include <nvgpu/nvgpu_mem.h>
33#include <nvgpu/allocator.h> 29#include <nvgpu/allocator.h>
34#include <nvgpu/vm.h> 30#include <nvgpu/vm.h>
@@ -36,17 +32,6 @@
36#include <nvgpu/rbtree.h> 32#include <nvgpu/rbtree.h>
37#include <nvgpu/kref.h> 33#include <nvgpu/kref.h>
38 34
39#ifdef CONFIG_ARM64
40#define outer_flush_range(a, b)
41#define __cpuc_flush_dcache_area __flush_dcache_area
42#endif
43
44#define FLUSH_CPU_DCACHE(va, pa, size) \
45 do { \
46 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \
47 outer_flush_range(pa, pa + (size_t)(size)); \
48 } while (0)
49
50struct gpfifo_desc { 35struct gpfifo_desc {
51 struct nvgpu_mem mem; 36 struct nvgpu_mem mem;
52 u32 entry_num; 37 u32 entry_num;
@@ -198,7 +183,4 @@ void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *mem,
198extern const struct gk20a_mmu_level gk20a_mm_levels_64k[]; 183extern const struct gk20a_mmu_level gk20a_mm_levels_64k[];
199extern const struct gk20a_mmu_level gk20a_mm_levels_128k[]; 184extern const struct gk20a_mmu_level gk20a_mm_levels_128k[];
200 185
201int gk20a_mm_get_buffer_info(struct device *dev, int dmabuf_fd,
202 u64 *buffer_id, u64 *buffer_len);
203
204#endif /* MM_GK20A_H */ 186#endif /* MM_GK20A_H */