gpu: nvgpu: Program NISO sysmem flush addr

Program sysmem flush address to prevent random accesses of
address 0.

Change-Id: I886170395f036805f02e0bce7ecd3c8c46b921df
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1129216
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>

1 files changed, 12 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index b5ec5e25..452d3e9c 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -424,6 +424,11 @@ static void gk20a_remove_mm_support(struct mm_gk20a *mm)
         gk20a_vm_remove_support_nofree(&mm->cde.vm);
 }
 
+static int gk20a_alloc_sysmem_flush(struct gk20a *g)
+{
+        return gk20a_gmmu_alloc(g, SZ_4K, &g->mm.sysmem_flush);
+}
+
 int gk20a_init_mm_setup_sw(struct gk20a *g)
 {
         struct mm_gk20a *mm = &g->mm;
@@ -447,6 +452,10 @@ int gk20a_init_mm_setup_sw(struct gk20a *g)
                        (int)(mm->channel.user_size >> 20),
                        (int)(mm->channel.kernel_size >> 20));
 
+        err = gk20a_alloc_sysmem_flush(g);
+        if (err)
+                return err;
+
         err = gk20a_init_bar1_vm(mm);
         if (err)
                 return err;
@@ -492,6 +501,9 @@ int gk20a_init_mm_setup_hw(struct gk20a *g)
                 mm->use_full_comp_tag_line =
                         g->ops.fb.set_use_full_comp_tag_line(g);
 
+        gk20a_writel(g, fb_niso_flush_sysmem_addr_r(),
+                     g->ops.mm.get_iova_addr(g, g->mm.sysmem_flush.sgt->sgl, 0)
+                     >> 8);
 
         g->ops.mm.bar1_bind(g, inst_pa);