summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
diff options
context:
space:
mode:
authorAlex Waterman <alexw@nvidia.com>2018-03-01 23:47:25 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-03-03 01:10:14 -0500
commit89fbf39a05483917c0a9f3453fd94c724bc37375 (patch)
tree55fdd147c0a7eb80b8fc50ecd9f4b0c80f1322f1 /drivers/gpu/nvgpu/gk20a/mm_gk20a.c
parentef116a6e632522def7493921666c3241318ce100 (diff)
Revert "Revert "gpu: nvgpu: Get coherency on gv100 + NVLINK working""
This reverts commit 5a35a95654d561fce09a3b9abf6b82bb7a29d74b. JIRA EVLR-2333 Change-Id: I923c32496c343d39d34f6d406c38a9f6ce7dc6e0 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1667167 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/mm_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/mm_gk20a.c24
1 files changed, 14 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index b27d1109..4ff6125b 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -122,8 +122,9 @@ static inline u32 big_valid_pde0_bits(struct gk20a *g,
122{ 122{
123 u32 pde0_bits = 123 u32 pde0_bits =
124 nvgpu_aperture_mask(g, pd->mem, 124 nvgpu_aperture_mask(g, pd->mem,
125 gmmu_pde_aperture_big_sys_mem_ncoh_f(), 125 gmmu_pde_aperture_big_sys_mem_ncoh_f(),
126 gmmu_pde_aperture_big_video_memory_f()) | 126 gmmu_pde_aperture_big_sys_mem_coh_f(),
127 gmmu_pde_aperture_big_video_memory_f()) |
127 gmmu_pde_address_big_sys_f( 128 gmmu_pde_address_big_sys_f(
128 (u32)(addr >> gmmu_pde_address_shift_v())); 129 (u32)(addr >> gmmu_pde_address_shift_v()));
129 130
@@ -135,8 +136,9 @@ static inline u32 small_valid_pde1_bits(struct gk20a *g,
135{ 136{
136 u32 pde1_bits = 137 u32 pde1_bits =
137 nvgpu_aperture_mask(g, pd->mem, 138 nvgpu_aperture_mask(g, pd->mem,
138 gmmu_pde_aperture_small_sys_mem_ncoh_f(), 139 gmmu_pde_aperture_small_sys_mem_ncoh_f(),
139 gmmu_pde_aperture_small_video_memory_f()) | 140 gmmu_pde_aperture_small_sys_mem_coh_f(),
141 gmmu_pde_aperture_small_video_memory_f()) |
140 gmmu_pde_vol_small_true_f() | /* tbd: why? */ 142 gmmu_pde_vol_small_true_f() | /* tbd: why? */
141 gmmu_pde_address_small_sys_f( 143 gmmu_pde_address_small_sys_f(
142 (u32)(addr >> gmmu_pde_address_shift_v())); 144 (u32)(addr >> gmmu_pde_address_shift_v()));
@@ -215,6 +217,7 @@ static void __update_pte(struct vm_gk20a *vm,
215 217
216 pte_w[1] = __nvgpu_aperture_mask(g, attrs->aperture, 218 pte_w[1] = __nvgpu_aperture_mask(g, attrs->aperture,
217 gmmu_pte_aperture_sys_mem_ncoh_f(), 219 gmmu_pte_aperture_sys_mem_ncoh_f(),
220 gmmu_pte_aperture_sys_mem_coh_f(),
218 gmmu_pte_aperture_video_memory_f()) | 221 gmmu_pte_aperture_video_memory_f()) |
219 gmmu_pte_kind_f(attrs->kind_v) | 222 gmmu_pte_kind_f(attrs->kind_v) |
220 gmmu_pte_comptagline_f((u32)(attrs->ctag >> ctag_shift)); 223 gmmu_pte_comptagline_f((u32)(attrs->ctag >> ctag_shift));
@@ -268,7 +271,7 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
268 page_size >> 10, 271 page_size >> 10,
269 nvgpu_gmmu_perm_str(attrs->rw_flag), 272 nvgpu_gmmu_perm_str(attrs->rw_flag),
270 attrs->kind_v, 273 attrs->kind_v,
271 nvgpu_aperture_str(attrs->aperture), 274 nvgpu_aperture_str(g, attrs->aperture),
272 attrs->cacheable ? 'C' : '-', 275 attrs->cacheable ? 'C' : '-',
273 attrs->sparse ? 'S' : '-', 276 attrs->sparse ? 'S' : '-',
274 attrs->priv ? 'P' : '-', 277 attrs->priv ? 'P' : '-',
@@ -363,11 +366,12 @@ void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
363 gk20a_dbg_info("pde pa=0x%llx", pdb_addr); 366 gk20a_dbg_info("pde pa=0x%llx", pdb_addr);
364 367
365 nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(), 368 nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(),
366 nvgpu_aperture_mask(g, vm->pdb.mem, 369 nvgpu_aperture_mask(g, vm->pdb.mem,
367 ram_in_page_dir_base_target_sys_mem_ncoh_f(), 370 ram_in_page_dir_base_target_sys_mem_ncoh_f(),
368 ram_in_page_dir_base_target_vid_mem_f()) | 371 ram_in_page_dir_base_target_sys_mem_coh_f(),
369 ram_in_page_dir_base_vol_true_f() | 372 ram_in_page_dir_base_target_vid_mem_f()) |
370 ram_in_page_dir_base_lo_f(pdb_addr_lo)); 373 ram_in_page_dir_base_vol_true_f() |
374 ram_in_page_dir_base_lo_f(pdb_addr_lo));
371 375
372 nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(), 376 nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(),
373 ram_in_page_dir_base_hi_f(pdb_addr_hi)); 377 ram_in_page_dir_base_hi_f(pdb_addr_hi));