gpu: nvgpu: Cleanup GMMU debug printing

Ensure that all debug prints are consistent from chip to chip
and function to function. The following maps letters in the
debug print to their meaning:

  C  Mapping is cachable
  v  Mapping is volatile
  S  Mapping is sparse
  P  Mapping is private (VPR/WPR)
  c  Mapping is coherent
  V  Mapping is valid

JIRA NVGPU-30

Change-Id: Ia890af88677c3e6d3fdd8c4fe266158c35b8afcd
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master/r/1514903
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Tested-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

1 files changed, 4 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index 0a84cabb..759e6a2b 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -1700,7 +1700,7 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
         pte_dbg(g, attrs,
                 "PTE: i=%-4u size=%-2u offs=%-4u | "
                 "GPU %#-12llx  phys %#-12llx "
-                "pgsz: %3dkb perm=%-2s kind=%#02x APT=%-6s %c%c%c%c "
+                "pgsz: %3dkb perm=%-2s kind=%#02x APT=%-6s %c%c%c%c%c "
                 "ctag=0x%08x "
                 "[0x%08x, 0x%08x]",
                 pd_idx, l->entry_size, pd_offset,
@@ -1709,10 +1709,11 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
                 nvgpu_gmmu_perm_str(attrs->rw_flag),
                 attrs->kind_v,
                 nvgpu_aperture_str(attrs->aperture),
-                attrs->valid     ? 'V' : '-',
-                attrs->cacheable ? 'C' : '-',
+                attrs->cacheable ? 'C' : 'v',
                 attrs->sparse    ? 'S' : '-',
                 attrs->priv      ? 'P' : '-',
+                attrs->coherent  ? 'c' : '-',
+                attrs->valid     ? 'V' : '-',
                 (u32)attrs->ctag >> ctag_shift,
                 pte_w[1], pte_w[0]);