diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-04-11 16:01:59 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-04-15 15:38:33 -0400 |
commit | 0e423669a4ff3f00b06d86f8ca251ef99f3671ce (patch) | |
tree | 637552c0c76d0a7a820d5cb8f359478d756e8c2a /drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |
parent | 7d8e2193893454bc8e05543c956fab32b8eed54b (diff) |
gpu: nvgpu: Wait for BAR1 bind
Wait for BAR1 bind to complete before continuing. The register to
wait exists Maxwell onwards.
Change-Id: Ie3736033fdb748c5da8d7a6085ad6d63acaf41f5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1123941
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/mm_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 5c3f83a6..b5ec5e25 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -493,15 +493,7 @@ int gk20a_init_mm_setup_hw(struct gk20a *g) | |||
493 | g->ops.fb.set_use_full_comp_tag_line(g); | 493 | g->ops.fb.set_use_full_comp_tag_line(g); |
494 | 494 | ||
495 | 495 | ||
496 | inst_pa = (u32)(inst_pa >> bar1_instance_block_shift_gk20a()); | 496 | g->ops.mm.bar1_bind(g, inst_pa); |
497 | gk20a_dbg_info("bar1 inst block ptr: 0x%08x", (u32)inst_pa); | ||
498 | |||
499 | gk20a_writel(g, bus_bar1_block_r(), | ||
500 | (g->mm.vidmem_is_vidmem ? | ||
501 | bus_bar1_block_target_sys_mem_ncoh_f() : | ||
502 | bus_bar1_block_target_vid_mem_f()) | | ||
503 | bus_bar1_block_mode_virtual_f() | | ||
504 | bus_bar1_block_ptr_f(inst_pa)); | ||
505 | 497 | ||
506 | if (g->ops.mm.init_bar2_mm_hw_setup) { | 498 | if (g->ops.mm.init_bar2_mm_hw_setup) { |
507 | err = g->ops.mm.init_bar2_mm_hw_setup(g); | 499 | err = g->ops.mm.init_bar2_mm_hw_setup(g); |
@@ -516,6 +508,21 @@ int gk20a_init_mm_setup_hw(struct gk20a *g) | |||
516 | return 0; | 508 | return 0; |
517 | } | 509 | } |
518 | 510 | ||
511 | static int gk20a_mm_bar1_bind(struct gk20a *g, u64 bar1_iova) | ||
512 | { | ||
513 | u64 inst_pa = (u32)(bar1_iova >> bar1_instance_block_shift_gk20a()); | ||
514 | gk20a_dbg_info("bar1 inst block ptr: 0x%08x", (u32)inst_pa); | ||
515 | |||
516 | gk20a_writel(g, bus_bar1_block_r(), | ||
517 | (g->mm.vidmem_is_vidmem ? | ||
518 | bus_bar1_block_target_sys_mem_ncoh_f() : | ||
519 | bus_bar1_block_target_vid_mem_f()) | | ||
520 | bus_bar1_block_mode_virtual_f() | | ||
521 | bus_bar1_block_ptr_f(inst_pa)); | ||
522 | |||
523 | return 0; | ||
524 | } | ||
525 | |||
519 | int gk20a_init_mm_support(struct gk20a *g) | 526 | int gk20a_init_mm_support(struct gk20a *g) |
520 | { | 527 | { |
521 | u32 err; | 528 | u32 err; |
@@ -3919,4 +3926,5 @@ void gk20a_init_mm(struct gpu_ops *gops) | |||
3919 | gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels; | 3926 | gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels; |
3920 | gops->mm.init_pdb = gk20a_mm_init_pdb; | 3927 | gops->mm.init_pdb = gk20a_mm_init_pdb; |
3921 | gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; | 3928 | gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; |
3929 | gops->mm.bar1_bind = gk20a_mm_bar1_bind; | ||
3922 | } | 3930 | } |