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authorVinod G <vinodg@nvidia.com>2018-05-16 13:43:13 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-05-18 17:53:58 -0400
commitac687c95d383c3fb0165e6535893510409559a8e (patch)
tree7a76099c05186ad636704c07c5409bbc8547f20f /drivers/gpu/nvgpu/gk20a/mc_gk20a.h
parentde67fb18fb639b7a605c77eeb2e1c639a8a3d67e (diff)
gpu: nvgpu: Code updates for MISRA violations
Code related to MC module is updated for handling MISRA violations Rule 10.1: Operands shalln't be an inappropriate essential type. Rule 10.3: Value of expression shalln't be assigned to an object with a narrow essential type. Rule 10.4: Both operands in an operator shall have the same essential type. Rule 14.4: Controlling if statement shall have essentially Boolean type. Rule 15.6: Enclose if() sequences with braces. JIRA NVGPU-646 JIRA NVGPU-659 JIRA NVGPU-671 Change-Id: Ia7ada40068eab5c164b8bad99bf8103b37a2fbc9 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1720926 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/mc_gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/mc_gk20a.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h b/drivers/gpu/nvgpu/gk20a/mc_gk20a.h
index 1ce308b8..1b59d634 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -32,7 +32,7 @@ u32 mc_gk20a_intr_stall(struct gk20a *g);
32void mc_gk20a_intr_stall_pause(struct gk20a *g); 32void mc_gk20a_intr_stall_pause(struct gk20a *g);
33void mc_gk20a_intr_stall_resume(struct gk20a *g); 33void mc_gk20a_intr_stall_resume(struct gk20a *g);
34u32 mc_gk20a_intr_nonstall(struct gk20a *g); 34u32 mc_gk20a_intr_nonstall(struct gk20a *g);
35int mc_gk20a_isr_nonstall(struct gk20a *g); 35u32 mc_gk20a_isr_nonstall(struct gk20a *g);
36void mc_gk20a_intr_nonstall_pause(struct gk20a *g); 36void mc_gk20a_intr_nonstall_pause(struct gk20a *g);
37void mc_gk20a_intr_nonstall_resume(struct gk20a *g); 37void mc_gk20a_intr_nonstall_resume(struct gk20a *g);
38void gk20a_mc_enable(struct gk20a *g, u32 units); 38void gk20a_mc_enable(struct gk20a *g, u32 units);
@@ -42,4 +42,4 @@ u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev);
42bool mc_gk20a_is_intr1_pending(struct gk20a *g, 42bool mc_gk20a_is_intr1_pending(struct gk20a *g,
43 enum nvgpu_unit unit, u32 mc_intr_1); 43 enum nvgpu_unit unit, u32 mc_intr_1);
44void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops); 44void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops);
45#endif 45#endif /* MC_GK20A_H */