diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-06-07 15:44:10 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-07 23:06:55 -0400 |
commit | fc724baa4becf051b3e6647858a6ded90f1cee86 (patch) | |
tree | 8d70e917e1aa5b7bf2bc97e1bc03838e38156916 /drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |
parent | 8efe596b01972c4efd39e709d51bd2e88a62d43f (diff) |
gpu: nvgpu: Add MC HAL is_intr1_pending
Add MC HAL is_intr1_pending. At the same time introduce nvgpu_unit
that is passed as parameter to is_intr1_pending. The API is passed
contents of intr1 register and an engine number, and returns true
if there's an interrupt pending for the engine.
JIRA NVGPU-26
Change-Id: I8e6363dd78572f8e41dbab2b258036ed168b6f75
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1497870
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/mc_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mc_gk20a.c | 28 |
1 files changed, 27 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c index bc11b14d..2cdcaaeb 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |||
@@ -20,6 +20,7 @@ | |||
20 | 20 | ||
21 | #include <nvgpu/timers.h> | 21 | #include <nvgpu/timers.h> |
22 | #include <nvgpu/atomic.h> | 22 | #include <nvgpu/atomic.h> |
23 | #include <nvgpu/unit.h> | ||
23 | 24 | ||
24 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | 25 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> |
25 | 26 | ||
@@ -134,7 +135,7 @@ void mc_gk20a_intr_thread_nonstall(struct gk20a *g, u32 mc_intr_1) | |||
134 | u32 engine_enum = ENGINE_INVAL_GK20A; | 135 | u32 engine_enum = ENGINE_INVAL_GK20A; |
135 | int ops_old, ops_new, ops = 0; | 136 | int ops_old, ops_new, ops = 0; |
136 | 137 | ||
137 | if (mc_intr_1 & mc_intr_0_pfifo_pending_f()) | 138 | if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1)) |
138 | ops |= gk20a_fifo_nonstall_isr(g); | 139 | ops |= gk20a_fifo_nonstall_isr(g); |
139 | 140 | ||
140 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; | 141 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; |
@@ -287,6 +288,30 @@ u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev) | |||
287 | return val; | 288 | return val; |
288 | } | 289 | } |
289 | 290 | ||
291 | bool mc_gk20a_is_intr1_pending(struct gk20a *g, | ||
292 | enum nvgpu_unit unit, u32 mc_intr_1) | ||
293 | { | ||
294 | u32 mask = 0; | ||
295 | bool is_pending; | ||
296 | |||
297 | switch (unit) { | ||
298 | case NVGPU_UNIT_FIFO: | ||
299 | mask = mc_intr_0_pfifo_pending_f(); | ||
300 | break; | ||
301 | default: | ||
302 | break; | ||
303 | } | ||
304 | |||
305 | if (mask == 0) { | ||
306 | nvgpu_err(g, "unknown unit %d", unit); | ||
307 | is_pending = false; | ||
308 | } else { | ||
309 | is_pending = (mc_intr_1 & mask) ? true : false; | ||
310 | } | ||
311 | |||
312 | return is_pending; | ||
313 | } | ||
314 | |||
290 | void gk20a_init_mc(struct gpu_ops *gops) | 315 | void gk20a_init_mc(struct gpu_ops *gops) |
291 | { | 316 | { |
292 | gops->mc.intr_enable = mc_gk20a_intr_enable; | 317 | gops->mc.intr_enable = mc_gk20a_intr_enable; |
@@ -302,4 +327,5 @@ void gk20a_init_mc(struct gpu_ops *gops) | |||
302 | gops->mc.disable = gk20a_mc_disable; | 327 | gops->mc.disable = gk20a_mc_disable; |
303 | gops->mc.reset = gk20a_mc_reset; | 328 | gops->mc.reset = gk20a_mc_reset; |
304 | gops->mc.boot_0 = gk20a_mc_boot_0; | 329 | gops->mc.boot_0 = gk20a_mc_boot_0; |
330 | gops->mc.is_intr1_pending = mc_gk20a_is_intr1_pending; | ||
305 | } | 331 | } |