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author | Rajkumar Kasirajan <rkasirajan@nvidia.com> | 2017-03-09 10:52:50 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-14 14:47:05 -0400 |
commit | e4a131a98d47740098c554425c532a2e3e48274d (patch) | |
tree | b385ca83be591e6dce7c009b65b06c3403c0c65a /drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |
parent | bf717d6273fa2d618dd2adf9bc349881f599e102 (diff) |
Revert "gpu: nvgpu: change stall intr handling order"
This reverts commit 35f0cf0efefe4a64ee25a5b118338b15e552dcb0 as
it caused lp0 suspend/resume failure.
Bug 1886110
Change-Id: Ib62207650344180361b6529f716f77b84528cd56
Signed-off-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
Reviewed-on: http://git-master/r/1317986
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/mc_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mc_gk20a.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c index caab6b5e..a1861b0d 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Master Control | 2 | * GK20A Master Control |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -121,12 +121,6 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g) | |||
121 | 121 | ||
122 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); | 122 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); |
123 | 123 | ||
124 | /* handle critical interrupts first */ | ||
125 | if (mc_intr_0 & mc_intr_0_pbus_pending_f()) | ||
126 | gk20a_pbus_isr(g); | ||
127 | if (mc_intr_0 & mc_intr_0_priv_ring_pending_f()) | ||
128 | gk20a_priv_ring_isr(g); | ||
129 | |||
130 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { | 124 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { |
131 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; | 125 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; |
132 | 126 | ||
@@ -151,8 +145,12 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g) | |||
151 | gk20a_fifo_isr(g); | 145 | gk20a_fifo_isr(g); |
152 | if (mc_intr_0 & mc_intr_0_pmu_pending_f()) | 146 | if (mc_intr_0 & mc_intr_0_pmu_pending_f()) |
153 | gk20a_pmu_isr(g); | 147 | gk20a_pmu_isr(g); |
148 | if (mc_intr_0 & mc_intr_0_priv_ring_pending_f()) | ||
149 | gk20a_priv_ring_isr(g); | ||
154 | if (mc_intr_0 & mc_intr_0_ltc_pending_f()) | 150 | if (mc_intr_0 & mc_intr_0_ltc_pending_f()) |
155 | g->ops.ltc.isr(g); | 151 | g->ops.ltc.isr(g); |
152 | if (mc_intr_0 & mc_intr_0_pbus_pending_f()) | ||
153 | gk20a_pbus_isr(g); | ||
156 | 154 | ||
157 | /* sync handled irq counter before re-enabling interrupts */ | 155 | /* sync handled irq counter before re-enabling interrupts */ |
158 | atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count); | 156 | atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count); |