diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-04-18 22:39:46 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-09 21:26:04 -0400 |
commit | dd739fcb039d51606e9a5454ec0aab17bcb01965 (patch) | |
tree | 806ba8575d146367ad1be00086ca0cdae35a6b28 /drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |
parent | 7e66f2a63d4855e763fa768047dfc32f6f96b771 (diff) |
gpu: nvgpu: Remove gk20a_dbg* functions
Switch all logging to nvgpu_log*(). gk20a_dbg* macros are
intentionally left there because of use from other repositories.
Because the new functions do not work without a pointer to struct
gk20a, and piping it just for logging is excessive, some log messages
are deleted.
Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704148
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/mc_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mc_gk20a.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c index 7fed410e..9473ad4f 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Master Control | 2 | * GK20A Master Control |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -40,7 +40,7 @@ void mc_gk20a_isr_stall(struct gk20a *g) | |||
40 | 40 | ||
41 | mc_intr_0 = g->ops.mc.intr_stall(g); | 41 | mc_intr_0 = g->ops.mc.intr_stall(g); |
42 | 42 | ||
43 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); | 43 | nvgpu_log(g, gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); |
44 | 44 | ||
45 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { | 45 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { |
46 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; | 46 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; |
@@ -200,7 +200,7 @@ void gk20a_mc_disable(struct gk20a *g, u32 units) | |||
200 | { | 200 | { |
201 | u32 pmc; | 201 | u32 pmc; |
202 | 202 | ||
203 | gk20a_dbg(gpu_dbg_info, "pmc disable: %08x\n", units); | 203 | nvgpu_log(g, gpu_dbg_info, "pmc disable: %08x\n", units); |
204 | 204 | ||
205 | nvgpu_spinlock_acquire(&g->mc_enable_lock); | 205 | nvgpu_spinlock_acquire(&g->mc_enable_lock); |
206 | pmc = gk20a_readl(g, mc_enable_r()); | 206 | pmc = gk20a_readl(g, mc_enable_r()); |
@@ -213,7 +213,7 @@ void gk20a_mc_enable(struct gk20a *g, u32 units) | |||
213 | { | 213 | { |
214 | u32 pmc; | 214 | u32 pmc; |
215 | 215 | ||
216 | gk20a_dbg(gpu_dbg_info, "pmc enable: %08x\n", units); | 216 | nvgpu_log(g, gpu_dbg_info, "pmc enable: %08x\n", units); |
217 | 217 | ||
218 | nvgpu_spinlock_acquire(&g->mc_enable_lock); | 218 | nvgpu_spinlock_acquire(&g->mc_enable_lock); |
219 | pmc = gk20a_readl(g, mc_enable_r()); | 219 | pmc = gk20a_readl(g, mc_enable_r()); |