gpu: nvgpu: disable ce2 interrupts when unhandled

ce2 interrupts enabled only on gk20a and gm20b when
interrupts are handled through hal

Change-Id: Ib570db8f5f41e71e768b95e781153ec8a5d20015
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/677447
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 6 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
index 86fea3a1..4aca3424 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
@@ -80,8 +80,9 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g)
 
         if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id))
                 gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g));
-        if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id))
-                gk20a_ce2_isr(g);
+        if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id)
+                && g->ops.ce2.isr_stall)
+                g->ops.ce2.isr_stall(g);
         if (mc_intr_0 & mc_intr_0_pfifo_pending_f())
                 gk20a_fifo_isr(g);
         if (mc_intr_0 & mc_intr_0_pmu_pending_f())
@@ -118,8 +119,9 @@ irqreturn_t mc_gk20a_intr_thread_nonstall(struct gk20a *g)
                 gk20a_fifo_nonstall_isr(g);
         if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id))
                 gk20a_gr_nonstall_isr(g);
-        if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id))
-                gk20a_ce2_nonstall_isr(g);
+        if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id)
+                && g->ops.ce2.isr_nonstall)
+                g->ops.ce2.isr_nonstall(g);
 
         gk20a_writel(g, mc_intr_en_1_r(),
                 mc_intr_en_1_inta_hardware_f());