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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-08-30 17:05:16 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-13 22:18:24 -0400
commit7ac0b046a538daa1a3532d3d5ae7cba1ef3295ba (patch)
tree79e42a4abe1e0c7d2918fa588f50061b90ee3e5f /drivers/gpu/nvgpu/gk20a/mc_gk20a.c
parentbf14c2a0faf922073eaf72d490bf8bde8df1a5c7 (diff)
gpu: nvgpu: Move MC HAL to common
Move implementation of MC HAL to common/mc. Also bump gk20a implementation to gm20b. gk20a_mc_boot_0 was used via a HAL, but we have only one possible implementation. It also has to be anyway called directly to detect which HALs to assign, so make it a true common function. mc_gk20a_handle_intr_nonstall was also used only in os/linux/intr.c so move it there. JIRA NVGPU-954 Change-Id: I79aedc9158f90d578db0edc17b714617b52690ac Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813519 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/mc_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/mc_gk20a.c331
1 files changed, 0 insertions, 331 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
deleted file mode 100644
index f9996e71..00000000
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ /dev/null
@@ -1,331 +0,0 @@
1/*
2 * GK20A Master Control
3 *
4 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "gk20a.h"
26#include "mc_gk20a.h"
27
28#include <nvgpu/timers.h>
29#include <nvgpu/atomic.h>
30#include <nvgpu/unit.h>
31#include <nvgpu/io.h>
32
33#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
34
35void mc_gk20a_isr_stall(struct gk20a *g)
36{
37 u32 mc_intr_0;
38 u32 engine_id_idx;
39 u32 active_engine_id = 0;
40 u32 engine_enum = ENGINE_INVAL_GK20A;
41
42 mc_intr_0 = g->ops.mc.intr_stall(g);
43
44 nvgpu_log(g, gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
45
46 for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
47 active_engine_id = g->fifo.active_engines_list[engine_id_idx];
48
49 if ((mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) != 0U) {
50 engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
51 /* GR Engine */
52 if (engine_enum == ENGINE_GR_GK20A) {
53 gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g));
54 }
55
56 /* CE Engine */
57 if (((engine_enum == ENGINE_GRCE_GK20A) ||
58 (engine_enum == ENGINE_ASYNC_CE_GK20A)) &&
59 (g->ops.ce2.isr_stall != NULL)) {
60 g->ops.ce2.isr_stall(g,
61 g->fifo.engine_info[active_engine_id].inst_id,
62 g->fifo.engine_info[active_engine_id].pri_base);
63 }
64 }
65 }
66 if ((mc_intr_0 & mc_intr_0_pfifo_pending_f()) != 0U) {
67 gk20a_fifo_isr(g);
68 }
69 if ((mc_intr_0 & mc_intr_0_pmu_pending_f()) != 0U) {
70 g->ops.pmu.pmu_isr(g);
71 }
72 if ((mc_intr_0 & mc_intr_0_priv_ring_pending_f()) != 0U) {
73 g->ops.priv_ring.isr(g);
74 }
75 if ((mc_intr_0 & mc_intr_0_ltc_pending_f()) != 0U) {
76 g->ops.ltc.isr(g);
77 }
78 if ((mc_intr_0 & mc_intr_0_pbus_pending_f()) != 0U) {
79 g->ops.bus.isr(g);
80 }
81}
82
83u32 mc_gk20a_isr_nonstall(struct gk20a *g)
84{
85 u32 ops = 0;
86 u32 mc_intr_1;
87 u32 engine_id_idx;
88 u32 active_engine_id = 0;
89 u32 engine_enum = ENGINE_INVAL_GK20A;
90
91 mc_intr_1 = g->ops.mc.intr_nonstall(g);
92
93 if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1) != 0U) {
94 ops |= gk20a_fifo_nonstall_isr(g);
95 }
96
97 for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines;
98 engine_id_idx++) {
99 struct fifo_engine_info_gk20a *engine_info;
100
101 active_engine_id = g->fifo.active_engines_list[engine_id_idx];
102 engine_info = &g->fifo.engine_info[active_engine_id];
103
104 if ((mc_intr_1 & engine_info->intr_mask) != 0U) {
105 engine_enum = engine_info->engine_enum;
106 /* GR Engine */
107 if (engine_enum == ENGINE_GR_GK20A) {
108 ops |= gk20a_gr_nonstall_isr(g);
109 }
110 /* CE Engine */
111 if (((engine_enum == ENGINE_GRCE_GK20A) ||
112 (engine_enum == ENGINE_ASYNC_CE_GK20A)) &&
113 (g->ops.ce2.isr_nonstall != NULL)) {
114 ops |= g->ops.ce2.isr_nonstall(g,
115 engine_info->inst_id,
116 engine_info->pri_base);
117 }
118 }
119 }
120
121 return ops;
122}
123
124void mc_gk20a_intr_mask(struct gk20a *g)
125{
126 nvgpu_writel(g, mc_intr_en_0_r(),
127 mc_intr_en_0_inta_disabled_f());
128 nvgpu_writel(g, mc_intr_en_1_r(),
129 mc_intr_en_1_inta_disabled_f());
130}
131
132void mc_gk20a_intr_enable(struct gk20a *g)
133{
134 u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
135
136 gk20a_writel(g, mc_intr_mask_1_r(),
137 mc_intr_0_pfifo_pending_f()
138 | eng_intr_mask);
139 gk20a_writel(g, mc_intr_en_1_r(),
140 mc_intr_en_1_inta_hardware_f());
141
142 gk20a_writel(g, mc_intr_mask_0_r(),
143 mc_intr_0_pfifo_pending_f()
144 | mc_intr_0_priv_ring_pending_f()
145 | mc_intr_0_ltc_pending_f()
146 | mc_intr_0_pbus_pending_f()
147 | eng_intr_mask);
148 gk20a_writel(g, mc_intr_en_0_r(),
149 mc_intr_en_0_inta_hardware_f());
150}
151
152void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable,
153 bool is_stalling, u32 mask)
154{
155 u32 mask_reg = (is_stalling ? mc_intr_mask_0_r() :
156 mc_intr_mask_1_r());
157
158 if (enable) {
159 gk20a_writel(g, mask_reg,
160 gk20a_readl(g, mask_reg) |
161 mask);
162 } else {
163 gk20a_writel(g, mask_reg,
164 gk20a_readl(g, mask_reg) &
165 ~mask);
166 }
167}
168
169void mc_gk20a_intr_stall_pause(struct gk20a *g)
170{
171 gk20a_writel(g, mc_intr_en_0_r(),
172 mc_intr_en_0_inta_disabled_f());
173
174 /* flush previous write */
175 (void) gk20a_readl(g, mc_intr_en_0_r());
176}
177
178void mc_gk20a_intr_stall_resume(struct gk20a *g)
179{
180 gk20a_writel(g, mc_intr_en_0_r(),
181 mc_intr_en_0_inta_hardware_f());
182
183 /* flush previous write */
184 (void) gk20a_readl(g, mc_intr_en_0_r());
185}
186
187void mc_gk20a_intr_nonstall_pause(struct gk20a *g)
188{
189 gk20a_writel(g, mc_intr_en_1_r(),
190 mc_intr_en_0_inta_disabled_f());
191
192 /* flush previous write */
193 (void) gk20a_readl(g, mc_intr_en_1_r());
194}
195
196void mc_gk20a_intr_nonstall_resume(struct gk20a *g)
197{
198 gk20a_writel(g, mc_intr_en_1_r(),
199 mc_intr_en_0_inta_hardware_f());
200
201 /* flush previous write */
202 (void) gk20a_readl(g, mc_intr_en_1_r());
203}
204
205u32 mc_gk20a_intr_stall(struct gk20a *g)
206{
207 return gk20a_readl(g, mc_intr_0_r());
208}
209
210u32 mc_gk20a_intr_nonstall(struct gk20a *g)
211{
212 return gk20a_readl(g, mc_intr_1_r());
213}
214
215void gk20a_mc_disable(struct gk20a *g, u32 units)
216{
217 u32 pmc;
218
219 nvgpu_log(g, gpu_dbg_info, "pmc disable: %08x\n", units);
220
221 nvgpu_spinlock_acquire(&g->mc_enable_lock);
222 pmc = gk20a_readl(g, mc_enable_r());
223 pmc &= ~units;
224 gk20a_writel(g, mc_enable_r(), pmc);
225 nvgpu_spinlock_release(&g->mc_enable_lock);
226}
227
228void gk20a_mc_enable(struct gk20a *g, u32 units)
229{
230 u32 pmc;
231
232 nvgpu_log(g, gpu_dbg_info, "pmc enable: %08x\n", units);
233
234 nvgpu_spinlock_acquire(&g->mc_enable_lock);
235 pmc = gk20a_readl(g, mc_enable_r());
236 pmc |= units;
237 gk20a_writel(g, mc_enable_r(), pmc);
238 pmc = gk20a_readl(g, mc_enable_r());
239 nvgpu_spinlock_release(&g->mc_enable_lock);
240
241 nvgpu_udelay(20);
242}
243
244void gk20a_mc_reset(struct gk20a *g, u32 units)
245{
246 g->ops.mc.disable(g, units);
247 if ((units & gk20a_fifo_get_all_ce_engine_reset_mask(g)) != 0U) {
248 nvgpu_udelay(500);
249 } else {
250 nvgpu_udelay(20);
251 }
252 g->ops.mc.enable(g, units);
253}
254
255u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev)
256{
257 u32 val = __nvgpu_readl(g, mc_boot_0_r());
258
259 if (val != 0xffffffffU) {
260
261 if (arch != NULL) {
262 *arch = mc_boot_0_architecture_v(val) <<
263 NVGPU_GPU_ARCHITECTURE_SHIFT;
264 }
265
266 if (impl != NULL) {
267 *impl = mc_boot_0_implementation_v(val);
268 }
269
270 if (rev != NULL) {
271 *rev = (mc_boot_0_major_revision_v(val) << 4) |
272 mc_boot_0_minor_revision_v(val);
273 }
274 }
275
276 return val;
277}
278
279bool mc_gk20a_is_intr1_pending(struct gk20a *g,
280 enum nvgpu_unit unit, u32 mc_intr_1)
281{
282 u32 mask = 0U;
283 bool is_pending;
284
285 switch (unit) {
286 case NVGPU_UNIT_FIFO:
287 mask = mc_intr_0_pfifo_pending_f();
288 break;
289 default:
290 break;
291 }
292
293 if (mask == 0U) {
294 nvgpu_err(g, "unknown unit %d", unit);
295 is_pending = false;
296 } else {
297 is_pending = ((mc_intr_1 & mask) != 0U) ? true : false;
298 }
299
300 return is_pending;
301}
302
303void mc_gk20a_log_pending_intrs(struct gk20a *g)
304{
305 u32 intr;
306
307 intr = g->ops.mc.intr_stall(g);
308 if (intr != 0U) {
309 nvgpu_info(g, "Pending stall intr0=0x%08x", intr);
310 }
311
312 intr = g->ops.mc.intr_nonstall(g);
313 if (intr != 0U) {
314 nvgpu_info(g, "Pending nonstall intr1=0x%08x", intr);
315 }
316}
317
318void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops)
319{
320 bool semaphore_wakeup, post_events;
321
322 semaphore_wakeup =
323 (((ops & GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE) != 0U) ?
324 true : false);
325 post_events = (((ops & GK20A_NONSTALL_OPS_POST_EVENTS) != 0U) ?
326 true: false);
327
328 if (semaphore_wakeup) {
329 g->ops.semaphore_wakeup(g, post_events);
330 }
331}
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