gpu: nvgpu: Split stalling interrupt handling

Split handling of stalling interrupt to Linux specific chip
agnostic and OS independent chip specific parts.

Linux specific chip independent part contains handler for ISR
and passing the control to a bottom half. It uses the new MC HALs
intr_stall (query interrupt status), intr_pause (pause interrupts)
and intr_resume (resume interrupts).

MC HAL isr_stall now returns void and gets called in thread context
and thus remove isr_thread_stall and replace the implementation with
isr_stall.

JIRA NVGPU-26

Change-Id: I206f330f6fc4a1f4def47c5f986585ac4080216d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1480243
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 29 insertions, 47 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
index ca7189cc..bc11b14d 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
@@ -1,7 +1,7 @@
 /*
  * GK20A Master Control
  *
- * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -41,33 +41,6 @@ void mc_gk20a_nonstall_cb(struct work_struct *work)
         } while (atomic_read(&g->nonstall_ops) != 0);
 }
 
-irqreturn_t mc_gk20a_isr_stall(struct gk20a *g)
-{
-        u32 mc_intr_0;
-
-        trace_mc_gk20a_intr_stall(g->name);
-
-        if (!g->power_on)
-                return IRQ_NONE;
-
-        /* not from gpu when sharing irq with others */
-        mc_intr_0 = gk20a_readl(g, mc_intr_0_r());
-        if (unlikely(!mc_intr_0))
-                return IRQ_NONE;
-
-        gk20a_writel(g, mc_intr_en_0_r(),
-                mc_intr_en_0_inta_disabled_f());
-
-        /* flush previous write */
-        gk20a_readl(g, mc_intr_en_0_r());
-
-        atomic_inc(&g->hw_irq_stall_count);
-
-        trace_mc_gk20a_intr_stall_done(g->name);
-
-        return IRQ_WAKE_THREAD;
-}
-
 irqreturn_t mc_gk20a_isr_nonstall(struct gk20a *g)
 {
         u32 mc_intr_1;
@@ -106,7 +79,7 @@ irqreturn_t mc_gk20a_isr_nonstall(struct gk20a *g)
         return IRQ_HANDLED;
 }
 
-irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g)
+void mc_gk20a_isr_stall(struct gk20a *g)
 {
         u32 mc_intr_0;
         int hw_irq_count;
@@ -114,11 +87,7 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g)
         u32 active_engine_id = 0;
         u32 engine_enum = ENGINE_INVAL_GK20A;
 
-        gk20a_dbg(gpu_dbg_intr, "interrupt thread launched");
-
-        trace_mc_gk20a_intr_thread_stall(g->name);
-
-        mc_intr_0 = gk20a_readl(g, mc_intr_0_r());
+        mc_intr_0 = g->ops.mc.intr_stall(g);
         hw_irq_count = atomic_read(&g->hw_irq_stall_count);
 
         gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
@@ -156,18 +125,6 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g)
 
         /* sync handled irq counter before re-enabling interrupts */
         atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count);
-
-        gk20a_writel(g, mc_intr_en_0_r(),
-                mc_intr_en_0_inta_hardware_f());
-
-        /* flush previous write */
-        gk20a_readl(g, mc_intr_en_0_r());
-
-        wake_up_all(&g->sw_irq_stall_last_handled_wq);
-
-        trace_mc_gk20a_intr_thread_stall_done(g->name);
-
-        return IRQ_HANDLED;
 }
 
 void mc_gk20a_intr_thread_nonstall(struct gk20a *g, u32 mc_intr_1)
@@ -250,6 +207,29 @@ void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable,
         }
 }
 
+void mc_gk20a_intr_stall_pause(struct gk20a *g)
+{
+        gk20a_writel(g, mc_intr_en_0_r(),
+                mc_intr_en_0_inta_disabled_f());
+
+        /* flush previous write */
+        gk20a_readl(g, mc_intr_en_0_r());
+}
+
+void mc_gk20a_intr_stall_resume(struct gk20a *g)
+{
+        gk20a_writel(g, mc_intr_en_0_r(),
+                mc_intr_en_0_inta_hardware_f());
+
+        /* flush previous write */
+        gk20a_readl(g, mc_intr_en_0_r());
+}
+
+u32 mc_gk20a_intr_stall(struct gk20a *g)
+{
+        return gk20a_readl(g, mc_intr_0_r());
+}
+
 void gk20a_mc_disable(struct gk20a *g, u32 units)
 {
         u32 pmc;
@@ -312,8 +292,10 @@ void gk20a_init_mc(struct gpu_ops *gops)
         gops->mc.intr_enable = mc_gk20a_intr_enable;
         gops->mc.intr_unit_config = mc_gk20a_intr_unit_config;
         gops->mc.isr_stall = mc_gk20a_isr_stall;
+        gops->mc.intr_stall = mc_gk20a_intr_stall;
+        gops->mc.intr_stall_pause = mc_gk20a_intr_stall_pause;
+        gops->mc.intr_stall_resume = mc_gk20a_intr_stall_resume;
         gops->mc.isr_nonstall = mc_gk20a_isr_nonstall;
-        gops->mc.isr_thread_stall = mc_gk20a_intr_thread_stall;
         gops->mc.isr_thread_nonstall = mc_gk20a_intr_thread_nonstall;
         gops->mc.isr_nonstall_cb = mc_gk20a_nonstall_cb;
         gops->mc.enable = gk20a_mc_enable;