gpu: nvgpu: add per-channel refcounting

Add reference counting for channels, and wait for reference count to
get to 0 in gk20a_channel_free() before actually freeing the channel.
Also, change free channel tracking a bit by employing a list of free
channels, which simplifies the procedure of finding available channels
with reference counting.

Each use of a channel must have a reference taken before use or held
by the caller. Taking a reference of a wild channel pointer may fail, if
the channel is either not opened or in a process of being closed. Also,
add safeguards for protecting accidental use of closed channels,
specifically, by setting ch->g = NULL in channel free. This will make it
obvious if freed channel is attempted to be used.

The last user of a channel might be the deferred interrupt handler,
so wait for deferred interrupts to be processed twice in the channel
free procedure: once for providing last notifications to the channel
and once to make sure there are no stale pointers left after referencing
to the channel has been denied.

Finally, fix some races in channel and TSG force reset IOCTL path,
by pausing the channel scheduler in gk20a_fifo_recover_ch() and
gk20a_fifo_recover_tsg(), while the affected engines have been identified,
the appropriate MMU faults triggered, and the MMU faults handled. In this
case, make sure that the MMU fault does not attempt to query the hardware
about the failing channel or TSG ids. This should make channel recovery
more safe also in the regular (i.e., not in the interrupt handler) context.

Bug 1530226
Bug 1597493
Bug 1625901
Bug 200076344
Bug 200071810

Change-Id: Ib274876908e18219c64ea41e50ca443df81d957b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/448463
(cherry picked from commit 3f03aeae64ef2af4829e06f5f63062e8ebd21353)
Reviewed-on: http://git-master/r/755147
Reviewed-by: Automatic_Commit_Validation_User

1 files changed, 18 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
index 06b00a25..0a773d10 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
@@ -40,6 +40,8 @@ irqreturn_t mc_gk20a_isr_stall(struct gk20a *g)
         /* flush previous write */
         gk20a_readl(g, mc_intr_en_0_r());
 
+        atomic_inc(&g->hw_irq_stall_count);
+
         trace_mc_gk20a_intr_stall_done(g->dev->name);
 
         return IRQ_WAKE_THREAD;
@@ -63,18 +65,22 @@ irqreturn_t mc_gk20a_isr_nonstall(struct gk20a *g)
         /* flush previous write */
         gk20a_readl(g, mc_intr_en_1_r());
 
+        atomic_inc(&g->hw_irq_nonstall_count);
+
         return IRQ_WAKE_THREAD;
 }
 
 irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g)
 {
         u32 mc_intr_0;
+        int hw_irq_count;
 
         gk20a_dbg(gpu_dbg_intr, "interrupt thread launched");
 
         trace_mc_gk20a_intr_thread_stall(g->dev->name);
 
         mc_intr_0 = gk20a_readl(g, mc_intr_0_r());
+        hw_irq_count = atomic_read(&g->hw_irq_stall_count);
 
         gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
 
@@ -94,12 +100,17 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g)
         if (mc_intr_0 & mc_intr_0_pbus_pending_f())
                 gk20a_pbus_isr(g);
 
+        /* sync handled irq counter before re-enabling interrupts */
+        atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count);
+
         gk20a_writel(g, mc_intr_en_0_r(),
                 mc_intr_en_0_inta_hardware_f());
 
         /* flush previous write */
         gk20a_readl(g, mc_intr_en_0_r());
 
+        wake_up_all(&g->sw_irq_stall_last_handled_wq);
+
         trace_mc_gk20a_intr_thread_stall_done(g->dev->name);
 
         return IRQ_HANDLED;
@@ -108,10 +119,12 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g)
 irqreturn_t mc_gk20a_intr_thread_nonstall(struct gk20a *g)
 {
         u32 mc_intr_1;
+        int hw_irq_count;
 
         gk20a_dbg(gpu_dbg_intr, "interrupt thread launched");
 
         mc_intr_1 = gk20a_readl(g, mc_intr_1_r());
+        hw_irq_count = atomic_read(&g->hw_irq_nonstall_count);
 
         gk20a_dbg(gpu_dbg_intr, "non-stall intr %08x\n", mc_intr_1);
 
@@ -125,12 +138,17 @@ irqreturn_t mc_gk20a_intr_thread_nonstall(struct gk20a *g)
                 && g->ops.ce2.isr_nonstall)
                 g->ops.ce2.isr_nonstall(g);
 
+        /* sync handled irq counter before re-enabling interrupts */
+        atomic_set(&g->sw_irq_nonstall_last_handled, hw_irq_count);
+
         gk20a_writel(g, mc_intr_en_1_r(),
                 mc_intr_en_1_inta_hardware_f());
 
         /* flush previous write */
         gk20a_readl(g, mc_intr_en_1_r());
 
+        wake_up_all(&g->sw_irq_stall_last_handled_wq);
+
         return IRQ_HANDLED;
 }