gpu: nvgpu: add HAL to handle nonstall interrupts

Add new HAL gops.mc.isr_nonstall() to handle nonstall interrupts

We already handle nonstall interrupts in nvgpu_intr_nonstall()
But this API is completely in linux specific code

Separate out os-independent code to handle nonstall interrupts in new API
mc_gk20a_isr_nonstall() and set it to HAL gops.mc.isr_nonstall() for all
existing chips

Call this HAL from nvgpu_intr_nonstall()

Jira NVGPUT-8

Change-Id: Iec6a56db03158a72a256f7eee8989a0a8a42ae2f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1706589
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 39 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
index e6d81a87..7fed410e 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
@@ -74,6 +74,45 @@ void mc_gk20a_isr_stall(struct gk20a *g)
                 g->ops.bus.isr(g);
 }
 
+int mc_gk20a_isr_nonstall(struct gk20a *g)
+{
+        int ops = 0;
+        u32 mc_intr_1;
+        u32 engine_id_idx;
+        u32 active_engine_id = 0;
+        u32 engine_enum = ENGINE_INVAL_GK20A;
+
+        mc_intr_1 = g->ops.mc.intr_nonstall(g);
+
+        if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1))
+                ops |= gk20a_fifo_nonstall_isr(g);
+
+        for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines;
+                                                        engine_id_idx++) {
+                struct fifo_engine_info_gk20a *engine_info;
+
+                active_engine_id = g->fifo.active_engines_list[engine_id_idx];
+                engine_info = &g->fifo.engine_info[active_engine_id];
+
+                if (mc_intr_1 & engine_info->intr_mask) {
+                        engine_enum = engine_info->engine_enum;
+                        /* GR Engine */
+                        if (engine_enum == ENGINE_GR_GK20A)
+                                ops |= gk20a_gr_nonstall_isr(g);
+
+                        /* CE Engine */
+                        if (((engine_enum == ENGINE_GRCE_GK20A) ||
+                             (engine_enum == ENGINE_ASYNC_CE_GK20A)) &&
+                              g->ops.ce2.isr_nonstall)
+                                ops |= g->ops.ce2.isr_nonstall(g,
+                                        engine_info->inst_id,
+                                        engine_info->pri_base);
+                }
+        }
+
+        return ops;
+}
+
 void mc_gk20a_intr_enable(struct gk20a *g)
 {
         u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);