gpu: nvgpu: switch gk20a nonstall ops to #defines

Fix MISRA rule 10.1 violations involving gk20a_nonstall_ops
enums by replacing them with with corresponding #defines.

Because these values can be used in expressions that require
unsigned values (e.g. bitwise OR) we cannot use enums.

The g->ce2.isr_nonstall() function was previously returning an
int that was a combination of gk20a_nonstall_ops enum bits which
led to the violations.

JIRA NVGPU-650

Change-Id: I6210aacec8829b3c8d339c5fe3db2f3069c67406
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796242
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
index 26084bd6..a0eae127 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
@@ -319,9 +319,10 @@ void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops)
 {
         bool semaphore_wakeup, post_events;
 
-        semaphore_wakeup = (((ops & (u32)gk20a_nonstall_ops_wakeup_semaphore) != 0U) ?
+        semaphore_wakeup =
+                (((ops & GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE) != 0U) ?
                                         true : false);
-        post_events = (((ops & (u32)gk20a_nonstall_ops_post_events) != 0U) ?
+        post_events = (((ops & GK20A_NONSTALL_OPS_POST_EVENTS) != 0U) ?
                                         true: false);
 
         if (semaphore_wakeup) {