diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-03-17 12:56:50 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-27 13:48:31 -0400 |
commit | b45a67934faeba042dbf6ebe47c520db3ef4090d (patch) | |
tree | 771f8c223a47281da915fee3348167724c332f56 /drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | |
parent | 0c45c5fcb60810f06b0ae05270f0fa7e32d31869 (diff) |
gpu: nvgpu: Use nvgpu_timeout for all loops
There were still a few remaining loops where we did not use
nvgpu_timeout and required Tegra specific functions for detecting if
timeout should be skipped. Replace all of them with nvgpu_timeout and
remove including chip-id.h where possible.
FE power mode timeout loop also used wrong delay value. It always
waited for the whole max timeout instead of looping with smaller
increments.
If SEC2 ACR boot fails to halt, we should not try to check ACR result
from mailbox. Add an early return for that case.
JIRA NVGPU-16
Change-Id: I9f0984250d7d01785755338e39822e6631dcaa5a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1323227
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/ltc_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c index 34a96971..9942e58f 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | |||
@@ -17,7 +17,9 @@ | |||
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include <linux/kernel.h> | 19 | #include <linux/kernel.h> |
20 | |||
20 | #include <trace/events/gk20a.h> | 21 | #include <trace/events/gk20a.h> |
22 | #include <nvgpu/timers.h> | ||
21 | 23 | ||
22 | #include "gk20a.h" | 24 | #include "gk20a.h" |
23 | 25 | ||
@@ -106,7 +108,6 @@ static int gk20a_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, | |||
106 | int err = 0; | 108 | int err = 0; |
107 | struct gr_gk20a *gr = &g->gr; | 109 | struct gr_gk20a *gr = &g->gr; |
108 | u32 fbp, slice, ctrl1, val, hw_op = 0; | 110 | u32 fbp, slice, ctrl1, val, hw_op = 0; |
109 | int retry = 200; | ||
110 | u32 slices_per_fbp = | 111 | u32 slices_per_fbp = |
111 | ltc_ltcs_ltss_cbc_param_slices_per_fbp_v( | 112 | ltc_ltcs_ltss_cbc_param_slices_per_fbp_v( |
112 | gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r())); | 113 | gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r())); |
@@ -140,6 +141,9 @@ static int gk20a_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, | |||
140 | gk20a_readl(g, ltc_ltcs_ltss_cbc_ctrl1_r()) | hw_op); | 141 | gk20a_readl(g, ltc_ltcs_ltss_cbc_ctrl1_r()) | hw_op); |
141 | 142 | ||
142 | for (fbp = 0; fbp < gr->num_fbps; fbp++) { | 143 | for (fbp = 0; fbp < gr->num_fbps; fbp++) { |
144 | struct nvgpu_timeout timeout; | ||
145 | |||
146 | nvgpu_timeout_init(g, &timeout, 200, NVGPU_TIMER_RETRY_TIMER); | ||
143 | for (slice = 0; slice < slices_per_fbp; slice++) { | 147 | for (slice = 0; slice < slices_per_fbp; slice++) { |
144 | 148 | ||
145 | 149 | ||
@@ -147,18 +151,15 @@ static int gk20a_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, | |||
147 | fbp * ltc_stride + | 151 | fbp * ltc_stride + |
148 | slice * lts_stride; | 152 | slice * lts_stride; |
149 | 153 | ||
150 | retry = 200; | ||
151 | do { | 154 | do { |
152 | val = gk20a_readl(g, ctrl1); | 155 | val = gk20a_readl(g, ctrl1); |
153 | if (!(val & hw_op)) | 156 | if (!(val & hw_op)) |
154 | break; | 157 | break; |
155 | retry--; | ||
156 | udelay(5); | 158 | udelay(5); |
157 | 159 | ||
158 | } while (retry >= 0 || | 160 | } while (!nvgpu_timeout_expired(&timeout)); |
159 | !tegra_platform_is_silicon()); | ||
160 | 161 | ||
161 | if (retry < 0 && tegra_platform_is_silicon()) { | 162 | if (nvgpu_timeout_peek_expired(&timeout)) { |
162 | gk20a_err(dev_from_gk20a(g), | 163 | gk20a_err(dev_from_gk20a(g), |
163 | "comp tag clear timeout\n"); | 164 | "comp tag clear timeout\n"); |
164 | err = -EBUSY; | 165 | err = -EBUSY; |