gpu: nvgpu: remove ltc_common.c

Remove ltc_common.c and integrate the included functions
into device specific ltc_gXXXX.c files. Merge non-device reg
definition dependent ltc functions into ltc_gk20a.c/h.

Prior to this patch, ltc_common.c was being directly included
into the device specific ltc source files as a workaround to
allow different devices to share the same code but still include
in different hw reg definitions.

Given that this approach was not adopted for other
systems, this code has been separated out for readability and
consistency.

Jira NVGPU-74

Change-Id: I4eea301927418532cc150b029535f165928cab89
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master/r/1507502
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 134 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
index 8867202f..1d517c27 100644
--- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
@@ -21,14 +21,36 @@
 #include <nvgpu/log.h>
 #include <nvgpu/bug.h>
 #include <nvgpu/enabled.h>
+#include <nvgpu/dma.h>
 
 #include "gk20a.h"
+#include "gr_gk20a.h"
 #include "ltc_gk20a.h"
 
 #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h>
 
-#include "ltc_common.c"
 
+/* Non HW reg dependent stuff: */
+
+int gk20a_ltc_alloc_phys_cbc(struct gk20a *g, size_t compbit_backing_size)
+{
+        struct gr_gk20a *gr = &g->gr;
+
+        return nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_FORCE_CONTIGUOUS,
+                                    compbit_backing_size,
+                                    &gr->compbit_store.mem);
+}
+
+int gk20a_ltc_alloc_virt_cbc(struct gk20a *g, size_t compbit_backing_size)
+{
+        struct gr_gk20a *gr = &g->gr;
+
+        return nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_NO_KERNEL_MAPPING,
+                                    compbit_backing_size,
+                                    &gr->compbit_store.mem);
+}
+
+/* HW reg dependent stuff: */
 static int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
 {
         /* max memory size (MB) to cover */
@@ -231,6 +253,117 @@ static int gk20a_determine_L2_size_bytes(struct gk20a *g)
         return cache_size;
 }
 
+/*
+ * Sets the ZBC color for the passed index.
+ */
+static void gk20a_ltc_set_zbc_color_entry(struct gk20a *g,
+                                          struct zbc_entry *color_val,
+                                          u32 index)
+{
+        u32 i;
+        u32 real_index = index + GK20A_STARTOF_ZBC_TABLE;
+
+        gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
+                     ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index));
+
+        for (i = 0;
+             i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) {
+                gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i),
+                             color_val->color_l2[i]);
+        }
+        gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r());
+}
+
+/*
+ * Sets the ZBC depth for the passed index.
+ */
+static void gk20a_ltc_set_zbc_depth_entry(struct gk20a *g,
+                                          struct zbc_entry *depth_val,
+                                          u32 index)
+{
+        u32 real_index = index + GK20A_STARTOF_ZBC_TABLE;
+
+        gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
+                     ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index));
+
+        gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(),
+                     depth_val->depth);
+
+        gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r());
+}
+
+static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
+{
+        u32 max_size = gr->max_comptag_mem;
+        u32 max_comptag_lines = max_size << 3;
+
+        u32 compbit_base_post_divide;
+        u64 compbit_base_post_multiply64;
+        u64 compbit_store_iova;
+        u64 compbit_base_post_divide64;
+
+        if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
+                compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem);
+        else
+                compbit_store_iova = g->ops.mm.get_iova_addr(g,
+                                gr->compbit_store.mem.priv.sgt->sgl, 0);
+
+        compbit_base_post_divide64 = compbit_store_iova >>
+                ltc_ltcs_ltss_cbc_base_alignment_shift_v();
+
+        do_div(compbit_base_post_divide64, g->ltc_count);
+        compbit_base_post_divide = u64_lo32(compbit_base_post_divide64);
+
+        compbit_base_post_multiply64 = ((u64)compbit_base_post_divide *
+                g->ltc_count) << ltc_ltcs_ltss_cbc_base_alignment_shift_v();
+
+        if (compbit_base_post_multiply64 < compbit_store_iova)
+                compbit_base_post_divide++;
+
+        /* Bug 1477079 indicates sw adjustment on the posted divided base. */
+        if (g->ops.ltc.cbc_fix_config)
+                compbit_base_post_divide =
+                        g->ops.ltc.cbc_fix_config(g, compbit_base_post_divide);
+
+        gk20a_writel(g, ltc_ltcs_ltss_cbc_base_r(),
+                compbit_base_post_divide);
+
+        gk20a_dbg(gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte,
+                   "compbit base.pa: 0x%x,%08x cbc_base:0x%08x\n",
+                   (u32)(compbit_store_iova >> 32),
+                   (u32)(compbit_store_iova & 0xffffffff),
+                   compbit_base_post_divide);
+
+        gr->compbit_store.base_hw = compbit_base_post_divide;
+
+        g->ops.ltc.cbc_ctrl(g, gk20a_cbc_op_invalidate,
+                            0, max_comptag_lines - 1);
+
+}
+
+#ifdef CONFIG_DEBUG_FS
+static void gk20a_ltc_sync_debugfs(struct gk20a *g)
+{
+        u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f();
+
+        nvgpu_spinlock_acquire(&g->debugfs_lock);
+        if (g->mm.ltc_enabled != g->mm.ltc_enabled_debug) {
+                u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r());
+
+                if (g->mm.ltc_enabled_debug)
+                        /* bypass disabled (normal caching ops)*/
+                        reg &= ~reg_f;
+                else
+                        /* bypass enabled (no caching) */
+                        reg |= reg_f;
+
+                gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg);
+                g->mm.ltc_enabled = g->mm.ltc_enabled_debug;
+        }
+        nvgpu_spinlock_release(&g->debugfs_lock);
+}
+#endif
+
 void gk20a_init_ltc(struct gpu_ops *gops)
 {
         gops->ltc.determine_L2_size_bytes = gk20a_determine_L2_size_bytes;