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authorTerje Bergstrom <tbergstrom@nvidia.com>2014-04-25 08:00:54 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:09:57 -0400
commit1c9aaa1eafcf91fbc29404b449f2bec072c804a5 (patch)
tree702f9933600962f05d0d76a9624a67f027b7bea8 /drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
parent24fc5e36a7f4fe2f36f78c6c91909595964f1645 (diff)
gpu: nvgpu: Implement ELPG flush for gm20b
ELPG flush is initiated from a common broadcast register, but must be waited on via per-L2 registers. Split gk20a and gm20b versions of the flush. Change-Id: I75c2d65e8da311b50d35bee70308b60464ec2d4d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/401545 Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/ltc_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/ltc_gk20a.c34
1 files changed, 34 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
index c1ba2aee..9f5317fc 100644
--- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
@@ -212,6 +212,40 @@ void gk20a_ltc_isr(struct gk20a *g)
212 gk20a_writel(g, ltc_ltc0_ltss_intr_r(), intr); 212 gk20a_writel(g, ltc_ltc0_ltss_intr_r(), intr);
213} 213}
214 214
215/* Flushes the compression bit cache as well as "data".
216 * Note: the name here is a bit of a misnomer. ELPG uses this
217 * internally... but ELPG doesn't have to be on to do it manually.
218 */
219static void gk20a_mm_g_elpg_flush_locked(struct gk20a *g)
220{
221 u32 data;
222 s32 retry = 100;
223
224 gk20a_dbg_fn("");
225
226 /* Make sure all previous writes are committed to the L2. There's no
227 guarantee that writes are to DRAM. This will be a sysmembar internal
228 to the L2. */
229 gk20a_writel(g, ltc_ltcs_ltss_g_elpg_r(),
230 ltc_ltcs_ltss_g_elpg_flush_pending_f());
231 do {
232 data = gk20a_readl(g, ltc_ltc0_ltss_g_elpg_r());
233
234 if (ltc_ltc0_ltss_g_elpg_flush_v(data) ==
235 ltc_ltc0_ltss_g_elpg_flush_pending_v()) {
236 gk20a_dbg_info("g_elpg_flush 0x%x", data);
237 retry--;
238 usleep_range(20, 40);
239 } else
240 break;
241 } while (retry >= 0 || !tegra_platform_is_silicon());
242
243 if (retry < 0)
244 gk20a_warn(dev_from_gk20a(g),
245 "g_elpg_flush too many retries");
246
247}
248
215void gk20a_init_ltc(struct gpu_ops *gops) 249void gk20a_init_ltc(struct gpu_ops *gops)
216{ 250{
217 gops->ltc.determine_L2_size_bytes = gk20a_determine_L2_size_bytes; 251 gops->ltc.determine_L2_size_bytes = gk20a_determine_L2_size_bytes;