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authorTerje Bergstrom <tbergstrom@nvidia.com>2015-03-20 12:43:26 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-04-04 22:01:53 -0400
commit42d17018b442850f246696364d79a2ae11350a12 (patch)
tree0ba6ca38145df8cab758cfa2b7bf50b5f825884a /drivers/gpu/nvgpu/gk20a/ltc_common.c
parent90e42e424aba21aed9aa380795cd564cfe97da28 (diff)
gpu: nvgpu: Use common allocator for compbit store
Reduce amount of duplicate code around memory allocation by using common helpers, and common data structure for storing results of allocations. Bug 1605769 Change-Id: I7c1662b669ed8c86465254f6001e536141051ee5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/720435
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/ltc_common.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/ltc_common.c95
1 files changed, 14 insertions, 81 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_common.c b/drivers/gpu/nvgpu/gk20a/ltc_common.c
index e230c4cd..f48f8298 100644
--- a/drivers/gpu/nvgpu/gk20a/ltc_common.c
+++ b/drivers/gpu/nvgpu/gk20a/ltc_common.c
@@ -77,87 +77,20 @@ static int gk20a_ltc_alloc_phys_cbc(struct gk20a *g,
77 size_t compbit_backing_size) 77 size_t compbit_backing_size)
78{ 78{
79 struct gr_gk20a *gr = &g->gr; 79 struct gr_gk20a *gr = &g->gr;
80 int order = order_base_2(compbit_backing_size >> PAGE_SHIFT);
81 struct page *pages;
82 struct sg_table *sgt;
83 int err = 0;
84
85 /* allocate pages */
86 pages = alloc_pages(GFP_KERNEL, order);
87 if (!pages) {
88 gk20a_dbg(gpu_dbg_pte, "alloc_pages failed\n");
89 err = -ENOMEM;
90 goto err_alloc_pages;
91 }
92
93 /* clean up the pages */
94 memset(page_address(pages), 0, compbit_backing_size);
95 80
96 /* allocate room for placing the pages pointer.. */ 81 return gk20a_gmmu_alloc_attr(g, DMA_ATTR_FORCE_CONTIGUOUS,
97 gr->compbit_store.pages = 82 compbit_backing_size,
98 kzalloc(sizeof(*gr->compbit_store.pages), GFP_KERNEL); 83 &gr->compbit_store.mem);
99 if (!gr->compbit_store.pages) {
100 gk20a_dbg(gpu_dbg_pte, "failed to allocate pages struct");
101 err = -ENOMEM;
102 goto err_alloc_compbit_store;
103 }
104
105 err = gk20a_get_sgtable_from_pages(&g->dev->dev, &sgt, &pages, 0,
106 compbit_backing_size);
107 if (err) {
108 gk20a_dbg(gpu_dbg_pte, "could not get sg table for pages\n");
109 goto err_alloc_sg_table;
110 }
111
112 /* store the parameters to gr structure */
113 *gr->compbit_store.pages = pages;
114 gr->compbit_store.base_iova = sg_phys(sgt->sgl);
115 gr->compbit_store.size = compbit_backing_size;
116 gr->compbit_store.sgt = sgt;
117
118 return 0;
119
120err_alloc_sg_table:
121 kfree(gr->compbit_store.pages);
122 gr->compbit_store.pages = NULL;
123err_alloc_compbit_store:
124 __free_pages(pages, order);
125err_alloc_pages:
126 return err;
127} 84}
128 85
129static int gk20a_ltc_alloc_virt_cbc(struct gk20a *g, 86static int gk20a_ltc_alloc_virt_cbc(struct gk20a *g,
130 size_t compbit_backing_size) 87 size_t compbit_backing_size)
131{ 88{
132 struct device *d = dev_from_gk20a(g);
133 struct gr_gk20a *gr = &g->gr; 89 struct gr_gk20a *gr = &g->gr;
134 DEFINE_DMA_ATTRS(attrs);
135 dma_addr_t iova;
136 int err;
137
138 dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
139
140 gr->compbit_store.pages =
141 dma_alloc_attrs(d, compbit_backing_size, &iova,
142 GFP_KERNEL, &attrs);
143 if (!gr->compbit_store.pages) {
144 gk20a_err(dev_from_gk20a(g), "failed to allocate backing store for compbit : size %zu",
145 compbit_backing_size);
146 return -ENOMEM;
147 }
148
149 gr->compbit_store.base_iova = iova;
150 gr->compbit_store.size = compbit_backing_size;
151 err = gk20a_get_sgtable_from_pages(d,
152 &gr->compbit_store.sgt,
153 gr->compbit_store.pages, iova,
154 compbit_backing_size);
155 if (err) {
156 gk20a_err(dev_from_gk20a(g), "failed to allocate sgt for backing store");
157 return err;
158 }
159 90
160 return 0; 91 return gk20a_gmmu_alloc_attr(g, DMA_ATTR_NO_KERNEL_MAPPING,
92 compbit_backing_size,
93 &gr->compbit_store.mem);
161} 94}
162 95
163static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) 96static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
@@ -167,16 +100,16 @@ static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
167 100
168 u32 compbit_base_post_divide; 101 u32 compbit_base_post_divide;
169 u64 compbit_base_post_multiply64; 102 u64 compbit_base_post_multiply64;
170 u64 compbit_store_base_iova; 103 u64 compbit_store_iova;
171 u64 compbit_base_post_divide64; 104 u64 compbit_base_post_divide64;
172 105
173 if (tegra_platform_is_linsim()) 106 if (tegra_platform_is_linsim())
174 compbit_store_base_iova = gr->compbit_store.base_iova; 107 compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem);
175 else 108 else
176 compbit_store_base_iova = gk20a_mm_smmu_vaddr_translate(g, 109 compbit_store_iova = gk20a_mm_iova_addr(g,
177 gr->compbit_store.base_iova); 110 gr->compbit_store.mem.sgt->sgl);
178 111
179 compbit_base_post_divide64 = compbit_store_base_iova >> 112 compbit_base_post_divide64 = compbit_store_iova >>
180 ltc_ltcs_ltss_cbc_base_alignment_shift_v(); 113 ltc_ltcs_ltss_cbc_base_alignment_shift_v();
181 114
182 do_div(compbit_base_post_divide64, g->ltc_count); 115 do_div(compbit_base_post_divide64, g->ltc_count);
@@ -185,7 +118,7 @@ static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
185 compbit_base_post_multiply64 = ((u64)compbit_base_post_divide * 118 compbit_base_post_multiply64 = ((u64)compbit_base_post_divide *
186 g->ltc_count) << ltc_ltcs_ltss_cbc_base_alignment_shift_v(); 119 g->ltc_count) << ltc_ltcs_ltss_cbc_base_alignment_shift_v();
187 120
188 if (compbit_base_post_multiply64 < compbit_store_base_iova) 121 if (compbit_base_post_multiply64 < compbit_store_iova)
189 compbit_base_post_divide++; 122 compbit_base_post_divide++;
190 123
191 /* Bug 1477079 indicates sw adjustment on the posted divided base. */ 124 /* Bug 1477079 indicates sw adjustment on the posted divided base. */
@@ -198,8 +131,8 @@ static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
198 131
199 gk20a_dbg(gpu_dbg_info | gpu_dbg_map | gpu_dbg_pte, 132 gk20a_dbg(gpu_dbg_info | gpu_dbg_map | gpu_dbg_pte,
200 "compbit base.pa: 0x%x,%08x cbc_base:0x%08x\n", 133 "compbit base.pa: 0x%x,%08x cbc_base:0x%08x\n",
201 (u32)(compbit_store_base_iova >> 32), 134 (u32)(compbit_store_iova >> 32),
202 (u32)(compbit_store_base_iova & 0xffffffff), 135 (u32)(compbit_store_iova & 0xffffffff),
203 compbit_base_post_divide); 136 compbit_base_post_divide);
204 137
205 gr->compbit_store.base_hw = compbit_base_post_divide; 138 gr->compbit_store.base_hw = compbit_base_post_divide;