gpu: nvgpu: Implement ELPG flush for gm20b

ELPG flush is initiated from a common broadcast register, but must be
waited on via per-L2 registers. Split gk20a and gm20b versions of
the flush.

Change-Id: I75c2d65e8da311b50d35bee70308b60464ec2d4d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/401545
Reviewed-by: Automatic_Commit_Validation_User

1 files changed, 0 insertions, 34 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/ltc_common.c b/drivers/gpu/nvgpu/gk20a/ltc_common.c
index ac46a9a0..72477983 100644
--- a/drivers/gpu/nvgpu/gk20a/ltc_common.c
+++ b/drivers/gpu/nvgpu/gk20a/ltc_common.c
@@ -313,37 +313,3 @@ static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
                             0, max_comptag_lines - 1);
 
 }
-
-/* Flushes the compression bit cache as well as "data".
- * Note: the name here is a bit of a misnomer.  ELPG uses this
- * internally... but ELPG doesn't have to be on to do it manually.
- */
-static void gk20a_mm_g_elpg_flush_locked(struct gk20a *g)
-{
-        u32 data;
-        s32 retry = 100;
-
-        gk20a_dbg_fn("");
-
-        /* Make sure all previous writes are committed to the L2. There's no
-           guarantee that writes are to DRAM. This will be a sysmembar internal
-           to the L2. */
-        gk20a_writel(g, ltc_ltcs_ltss_g_elpg_r(),
-                     ltc_ltcs_ltss_g_elpg_flush_pending_f());
-        do {
-                data = gk20a_readl(g, ltc_ltc0_ltss_g_elpg_r());
-
-                if (ltc_ltc0_ltss_g_elpg_flush_v(data) ==
-                    ltc_ltc0_ltss_g_elpg_flush_pending_v()) {
-                        gk20a_dbg_info("g_elpg_flush 0x%x", data);
-                        retry--;
-                        usleep_range(20, 40);
-                } else
-                        break;
-        } while (retry >= 0 || !tegra_platform_is_silicon());
-
-        if (retry < 0)
-                gk20a_warn(dev_from_gk20a(g),
-                            "g_elpg_flush too many retries");
-
-}