gpu: nvgpu: Sync gk20a and gm20b headers

Synchronize gk20a and gm20b headers. All registers which were added
to gk20a are now added to gm20b, and some registers that are unused
are removed.

Bug 1567274

Change-Id: Ia3b7958c148e495cbff420ee56bb448db0f58680
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590313
GVS: Gerrit_Virtual_Submit

1 files changed, 9 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/hw_trim_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_trim_gk20a.h
index 826e9bd1..3b0aa05b 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_trim_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_trim_gk20a.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -110,6 +110,10 @@ static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v)
 {
         return (v & 0xff) << 0;
 }
+static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void)
+{
+        return 0xff << 0;
+}
 static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r)
 {
         return (r >> 0) & 0xff;
@@ -130,6 +134,10 @@ static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v)
 {
         return (v & 0x3f) << 16;
 }
+static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void)
+{
+        return 0x3f << 16;
+}
 static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r)
 {
         return (r >> 16) & 0x3f;