diff options
author | Alex Waterman <alexw@nvidia.com> | 2016-10-28 19:49:50 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-01-11 15:44:14 -0500 |
commit | b928f10d37bdb57266569073d8b5d553dbf39044 (patch) | |
tree | 60da9d9344963bfac157d91e74107d49109ef9a5 /drivers/gpu/nvgpu/gk20a/hw_sim_gk20a.h | |
parent | 5e68c6e971d98fc9d4beaf69c5ca58f39f8db1a7 (diff) |
gpu: nvgpu: Start re-organizing the HW headers
Reorganize the HW headers of gk20a. The headers are moved to a
new directory:
include/nvgpu/hw/gk20a
And from the code are included like so:
#include <nvgpu/hw/gk20a/hw_pwr_gk20a.h>
This is the first step in reorganizing all of the HW headers for
gm20b, gm206, etc. This is part of a larger effort to re-structure
and make the driver more readable and scalable.
Bug 1799159
Change-Id: Ic151155cbc2e6f75009f2d9d597b364a1bed2c4c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1244790
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/hw_sim_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_sim_gk20a.h | 2150 |
1 files changed, 0 insertions, 2150 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/hw_sim_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_sim_gk20a.h deleted file mode 100644 index b1e6658d..00000000 --- a/drivers/gpu/nvgpu/gk20a/hw_sim_gk20a.h +++ /dev/null | |||
@@ -1,2150 +0,0 @@ | |||
1 | /* | ||
2 | * drivers/video/tegra/host/gk20a/hw_sim_gk20a.h | ||
3 | * | ||
4 | * Copyright (c) 2012, NVIDIA Corporation. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | * | ||
18 | */ | ||
19 | |||
20 | /* | ||
21 | * Function naming determines intended use: | ||
22 | * | ||
23 | * <x>_r(void) : Returns the offset for register <x>. | ||
24 | * | ||
25 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
26 | * | ||
27 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
28 | * | ||
29 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
30 | * and masked to place it at field <y> of register <x>. This value | ||
31 | * can be |'d with others to produce a full register value for | ||
32 | * register <x>. | ||
33 | * | ||
34 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
35 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
39 | * to place it at field <y> of register <x>. This value can be |'d | ||
40 | * with others to produce a full register value for <x>. | ||
41 | * | ||
42 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
43 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
44 | * This value is suitable for direct comparison with other unshifted | ||
45 | * values appropriate for use in field <y> of register <x>. | ||
46 | * | ||
47 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
48 | * field <y> of register <x>. This value is suitable for direct | ||
49 | * comparison with unshifted values appropriate for use in field <y> | ||
50 | * of register <x>. | ||
51 | */ | ||
52 | |||
53 | #ifndef __hw_sim_gk20a_h__ | ||
54 | #define __hw_sim_gk20a_h__ | ||
55 | /*This file is autogenerated. Do not edit. */ | ||
56 | |||
57 | static inline u32 sim_send_ring_r(void) | ||
58 | { | ||
59 | return 0x00000000; | ||
60 | } | ||
61 | static inline u32 sim_send_ring_target_s(void) | ||
62 | { | ||
63 | return 2; | ||
64 | } | ||
65 | static inline u32 sim_send_ring_target_f(u32 v) | ||
66 | { | ||
67 | return (v & 0x3) << 0; | ||
68 | } | ||
69 | static inline u32 sim_send_ring_target_m(void) | ||
70 | { | ||
71 | return 0x3 << 0; | ||
72 | } | ||
73 | static inline u32 sim_send_ring_target_v(u32 r) | ||
74 | { | ||
75 | return (r >> 0) & 0x3; | ||
76 | } | ||
77 | static inline u32 sim_send_ring_target_phys_init_v(void) | ||
78 | { | ||
79 | return 0x00000001; | ||
80 | } | ||
81 | static inline u32 sim_send_ring_target_phys_init_f(void) | ||
82 | { | ||
83 | return 0x1; | ||
84 | } | ||
85 | static inline u32 sim_send_ring_target_phys__init_v(void) | ||
86 | { | ||
87 | return 0x00000001; | ||
88 | } | ||
89 | static inline u32 sim_send_ring_target_phys__init_f(void) | ||
90 | { | ||
91 | return 0x1; | ||
92 | } | ||
93 | static inline u32 sim_send_ring_target_phys__prod_v(void) | ||
94 | { | ||
95 | return 0x00000001; | ||
96 | } | ||
97 | static inline u32 sim_send_ring_target_phys__prod_f(void) | ||
98 | { | ||
99 | return 0x1; | ||
100 | } | ||
101 | static inline u32 sim_send_ring_target_phys_nvm_v(void) | ||
102 | { | ||
103 | return 0x00000001; | ||
104 | } | ||
105 | static inline u32 sim_send_ring_target_phys_nvm_f(void) | ||
106 | { | ||
107 | return 0x1; | ||
108 | } | ||
109 | static inline u32 sim_send_ring_target_phys_pci_v(void) | ||
110 | { | ||
111 | return 0x00000002; | ||
112 | } | ||
113 | static inline u32 sim_send_ring_target_phys_pci_f(void) | ||
114 | { | ||
115 | return 0x2; | ||
116 | } | ||
117 | static inline u32 sim_send_ring_target_phys_pci_coherent_v(void) | ||
118 | { | ||
119 | return 0x00000003; | ||
120 | } | ||
121 | static inline u32 sim_send_ring_target_phys_pci_coherent_f(void) | ||
122 | { | ||
123 | return 0x3; | ||
124 | } | ||
125 | static inline u32 sim_send_ring_status_s(void) | ||
126 | { | ||
127 | return 1; | ||
128 | } | ||
129 | static inline u32 sim_send_ring_status_f(u32 v) | ||
130 | { | ||
131 | return (v & 0x1) << 3; | ||
132 | } | ||
133 | static inline u32 sim_send_ring_status_m(void) | ||
134 | { | ||
135 | return 0x1 << 3; | ||
136 | } | ||
137 | static inline u32 sim_send_ring_status_v(u32 r) | ||
138 | { | ||
139 | return (r >> 3) & 0x1; | ||
140 | } | ||
141 | static inline u32 sim_send_ring_status_init_v(void) | ||
142 | { | ||
143 | return 0x00000000; | ||
144 | } | ||
145 | static inline u32 sim_send_ring_status_init_f(void) | ||
146 | { | ||
147 | return 0x0; | ||
148 | } | ||
149 | static inline u32 sim_send_ring_status__init_v(void) | ||
150 | { | ||
151 | return 0x00000000; | ||
152 | } | ||
153 | static inline u32 sim_send_ring_status__init_f(void) | ||
154 | { | ||
155 | return 0x0; | ||
156 | } | ||
157 | static inline u32 sim_send_ring_status__prod_v(void) | ||
158 | { | ||
159 | return 0x00000000; | ||
160 | } | ||
161 | static inline u32 sim_send_ring_status__prod_f(void) | ||
162 | { | ||
163 | return 0x0; | ||
164 | } | ||
165 | static inline u32 sim_send_ring_status_invalid_v(void) | ||
166 | { | ||
167 | return 0x00000000; | ||
168 | } | ||
169 | static inline u32 sim_send_ring_status_invalid_f(void) | ||
170 | { | ||
171 | return 0x0; | ||
172 | } | ||
173 | static inline u32 sim_send_ring_status_valid_v(void) | ||
174 | { | ||
175 | return 0x00000001; | ||
176 | } | ||
177 | static inline u32 sim_send_ring_status_valid_f(void) | ||
178 | { | ||
179 | return 0x8; | ||
180 | } | ||
181 | static inline u32 sim_send_ring_size_s(void) | ||
182 | { | ||
183 | return 2; | ||
184 | } | ||
185 | static inline u32 sim_send_ring_size_f(u32 v) | ||
186 | { | ||
187 | return (v & 0x3) << 4; | ||
188 | } | ||
189 | static inline u32 sim_send_ring_size_m(void) | ||
190 | { | ||
191 | return 0x3 << 4; | ||
192 | } | ||
193 | static inline u32 sim_send_ring_size_v(u32 r) | ||
194 | { | ||
195 | return (r >> 4) & 0x3; | ||
196 | } | ||
197 | static inline u32 sim_send_ring_size_init_v(void) | ||
198 | { | ||
199 | return 0x00000000; | ||
200 | } | ||
201 | static inline u32 sim_send_ring_size_init_f(void) | ||
202 | { | ||
203 | return 0x0; | ||
204 | } | ||
205 | static inline u32 sim_send_ring_size__init_v(void) | ||
206 | { | ||
207 | return 0x00000000; | ||
208 | } | ||
209 | static inline u32 sim_send_ring_size__init_f(void) | ||
210 | { | ||
211 | return 0x0; | ||
212 | } | ||
213 | static inline u32 sim_send_ring_size__prod_v(void) | ||
214 | { | ||
215 | return 0x00000000; | ||
216 | } | ||
217 | static inline u32 sim_send_ring_size__prod_f(void) | ||
218 | { | ||
219 | return 0x0; | ||
220 | } | ||
221 | static inline u32 sim_send_ring_size_4kb_v(void) | ||
222 | { | ||
223 | return 0x00000000; | ||
224 | } | ||
225 | static inline u32 sim_send_ring_size_4kb_f(void) | ||
226 | { | ||
227 | return 0x0; | ||
228 | } | ||
229 | static inline u32 sim_send_ring_size_8kb_v(void) | ||
230 | { | ||
231 | return 0x00000001; | ||
232 | } | ||
233 | static inline u32 sim_send_ring_size_8kb_f(void) | ||
234 | { | ||
235 | return 0x10; | ||
236 | } | ||
237 | static inline u32 sim_send_ring_size_12kb_v(void) | ||
238 | { | ||
239 | return 0x00000002; | ||
240 | } | ||
241 | static inline u32 sim_send_ring_size_12kb_f(void) | ||
242 | { | ||
243 | return 0x20; | ||
244 | } | ||
245 | static inline u32 sim_send_ring_size_16kb_v(void) | ||
246 | { | ||
247 | return 0x00000003; | ||
248 | } | ||
249 | static inline u32 sim_send_ring_size_16kb_f(void) | ||
250 | { | ||
251 | return 0x30; | ||
252 | } | ||
253 | static inline u32 sim_send_ring_gp_in_ring_s(void) | ||
254 | { | ||
255 | return 1; | ||
256 | } | ||
257 | static inline u32 sim_send_ring_gp_in_ring_f(u32 v) | ||
258 | { | ||
259 | return (v & 0x1) << 11; | ||
260 | } | ||
261 | static inline u32 sim_send_ring_gp_in_ring_m(void) | ||
262 | { | ||
263 | return 0x1 << 11; | ||
264 | } | ||
265 | static inline u32 sim_send_ring_gp_in_ring_v(u32 r) | ||
266 | { | ||
267 | return (r >> 11) & 0x1; | ||
268 | } | ||
269 | static inline u32 sim_send_ring_gp_in_ring__init_v(void) | ||
270 | { | ||
271 | return 0x00000000; | ||
272 | } | ||
273 | static inline u32 sim_send_ring_gp_in_ring__init_f(void) | ||
274 | { | ||
275 | return 0x0; | ||
276 | } | ||
277 | static inline u32 sim_send_ring_gp_in_ring__prod_v(void) | ||
278 | { | ||
279 | return 0x00000000; | ||
280 | } | ||
281 | static inline u32 sim_send_ring_gp_in_ring__prod_f(void) | ||
282 | { | ||
283 | return 0x0; | ||
284 | } | ||
285 | static inline u32 sim_send_ring_gp_in_ring_no_v(void) | ||
286 | { | ||
287 | return 0x00000000; | ||
288 | } | ||
289 | static inline u32 sim_send_ring_gp_in_ring_no_f(void) | ||
290 | { | ||
291 | return 0x0; | ||
292 | } | ||
293 | static inline u32 sim_send_ring_gp_in_ring_yes_v(void) | ||
294 | { | ||
295 | return 0x00000001; | ||
296 | } | ||
297 | static inline u32 sim_send_ring_gp_in_ring_yes_f(void) | ||
298 | { | ||
299 | return 0x800; | ||
300 | } | ||
301 | static inline u32 sim_send_ring_addr_lo_s(void) | ||
302 | { | ||
303 | return 20; | ||
304 | } | ||
305 | static inline u32 sim_send_ring_addr_lo_f(u32 v) | ||
306 | { | ||
307 | return (v & 0xfffff) << 12; | ||
308 | } | ||
309 | static inline u32 sim_send_ring_addr_lo_m(void) | ||
310 | { | ||
311 | return 0xfffff << 12; | ||
312 | } | ||
313 | static inline u32 sim_send_ring_addr_lo_v(u32 r) | ||
314 | { | ||
315 | return (r >> 12) & 0xfffff; | ||
316 | } | ||
317 | static inline u32 sim_send_ring_addr_lo__init_v(void) | ||
318 | { | ||
319 | return 0x00000000; | ||
320 | } | ||
321 | static inline u32 sim_send_ring_addr_lo__init_f(void) | ||
322 | { | ||
323 | return 0x0; | ||
324 | } | ||
325 | static inline u32 sim_send_ring_addr_lo__prod_v(void) | ||
326 | { | ||
327 | return 0x00000000; | ||
328 | } | ||
329 | static inline u32 sim_send_ring_addr_lo__prod_f(void) | ||
330 | { | ||
331 | return 0x0; | ||
332 | } | ||
333 | static inline u32 sim_send_ring_hi_r(void) | ||
334 | { | ||
335 | return 0x00000004; | ||
336 | } | ||
337 | static inline u32 sim_send_ring_hi_addr_s(void) | ||
338 | { | ||
339 | return 20; | ||
340 | } | ||
341 | static inline u32 sim_send_ring_hi_addr_f(u32 v) | ||
342 | { | ||
343 | return (v & 0xfffff) << 0; | ||
344 | } | ||
345 | static inline u32 sim_send_ring_hi_addr_m(void) | ||
346 | { | ||
347 | return 0xfffff << 0; | ||
348 | } | ||
349 | static inline u32 sim_send_ring_hi_addr_v(u32 r) | ||
350 | { | ||
351 | return (r >> 0) & 0xfffff; | ||
352 | } | ||
353 | static inline u32 sim_send_ring_hi_addr__init_v(void) | ||
354 | { | ||
355 | return 0x00000000; | ||
356 | } | ||
357 | static inline u32 sim_send_ring_hi_addr__init_f(void) | ||
358 | { | ||
359 | return 0x0; | ||
360 | } | ||
361 | static inline u32 sim_send_ring_hi_addr__prod_v(void) | ||
362 | { | ||
363 | return 0x00000000; | ||
364 | } | ||
365 | static inline u32 sim_send_ring_hi_addr__prod_f(void) | ||
366 | { | ||
367 | return 0x0; | ||
368 | } | ||
369 | static inline u32 sim_send_put_r(void) | ||
370 | { | ||
371 | return 0x00000008; | ||
372 | } | ||
373 | static inline u32 sim_send_put_pointer_s(void) | ||
374 | { | ||
375 | return 29; | ||
376 | } | ||
377 | static inline u32 sim_send_put_pointer_f(u32 v) | ||
378 | { | ||
379 | return (v & 0x1fffffff) << 3; | ||
380 | } | ||
381 | static inline u32 sim_send_put_pointer_m(void) | ||
382 | { | ||
383 | return 0x1fffffff << 3; | ||
384 | } | ||
385 | static inline u32 sim_send_put_pointer_v(u32 r) | ||
386 | { | ||
387 | return (r >> 3) & 0x1fffffff; | ||
388 | } | ||
389 | static inline u32 sim_send_get_r(void) | ||
390 | { | ||
391 | return 0x0000000c; | ||
392 | } | ||
393 | static inline u32 sim_send_get_pointer_s(void) | ||
394 | { | ||
395 | return 29; | ||
396 | } | ||
397 | static inline u32 sim_send_get_pointer_f(u32 v) | ||
398 | { | ||
399 | return (v & 0x1fffffff) << 3; | ||
400 | } | ||
401 | static inline u32 sim_send_get_pointer_m(void) | ||
402 | { | ||
403 | return 0x1fffffff << 3; | ||
404 | } | ||
405 | static inline u32 sim_send_get_pointer_v(u32 r) | ||
406 | { | ||
407 | return (r >> 3) & 0x1fffffff; | ||
408 | } | ||
409 | static inline u32 sim_recv_ring_r(void) | ||
410 | { | ||
411 | return 0x00000010; | ||
412 | } | ||
413 | static inline u32 sim_recv_ring_target_s(void) | ||
414 | { | ||
415 | return 2; | ||
416 | } | ||
417 | static inline u32 sim_recv_ring_target_f(u32 v) | ||
418 | { | ||
419 | return (v & 0x3) << 0; | ||
420 | } | ||
421 | static inline u32 sim_recv_ring_target_m(void) | ||
422 | { | ||
423 | return 0x3 << 0; | ||
424 | } | ||
425 | static inline u32 sim_recv_ring_target_v(u32 r) | ||
426 | { | ||
427 | return (r >> 0) & 0x3; | ||
428 | } | ||
429 | static inline u32 sim_recv_ring_target_phys_init_v(void) | ||
430 | { | ||
431 | return 0x00000001; | ||
432 | } | ||
433 | static inline u32 sim_recv_ring_target_phys_init_f(void) | ||
434 | { | ||
435 | return 0x1; | ||
436 | } | ||
437 | static inline u32 sim_recv_ring_target_phys__init_v(void) | ||
438 | { | ||
439 | return 0x00000001; | ||
440 | } | ||
441 | static inline u32 sim_recv_ring_target_phys__init_f(void) | ||
442 | { | ||
443 | return 0x1; | ||
444 | } | ||
445 | static inline u32 sim_recv_ring_target_phys__prod_v(void) | ||
446 | { | ||
447 | return 0x00000001; | ||
448 | } | ||
449 | static inline u32 sim_recv_ring_target_phys__prod_f(void) | ||
450 | { | ||
451 | return 0x1; | ||
452 | } | ||
453 | static inline u32 sim_recv_ring_target_phys_nvm_v(void) | ||
454 | { | ||
455 | return 0x00000001; | ||
456 | } | ||
457 | static inline u32 sim_recv_ring_target_phys_nvm_f(void) | ||
458 | { | ||
459 | return 0x1; | ||
460 | } | ||
461 | static inline u32 sim_recv_ring_target_phys_pci_v(void) | ||
462 | { | ||
463 | return 0x00000002; | ||
464 | } | ||
465 | static inline u32 sim_recv_ring_target_phys_pci_f(void) | ||
466 | { | ||
467 | return 0x2; | ||
468 | } | ||
469 | static inline u32 sim_recv_ring_target_phys_pci_coherent_v(void) | ||
470 | { | ||
471 | return 0x00000003; | ||
472 | } | ||
473 | static inline u32 sim_recv_ring_target_phys_pci_coherent_f(void) | ||
474 | { | ||
475 | return 0x3; | ||
476 | } | ||
477 | static inline u32 sim_recv_ring_status_s(void) | ||
478 | { | ||
479 | return 1; | ||
480 | } | ||
481 | static inline u32 sim_recv_ring_status_f(u32 v) | ||
482 | { | ||
483 | return (v & 0x1) << 3; | ||
484 | } | ||
485 | static inline u32 sim_recv_ring_status_m(void) | ||
486 | { | ||
487 | return 0x1 << 3; | ||
488 | } | ||
489 | static inline u32 sim_recv_ring_status_v(u32 r) | ||
490 | { | ||
491 | return (r >> 3) & 0x1; | ||
492 | } | ||
493 | static inline u32 sim_recv_ring_status_init_v(void) | ||
494 | { | ||
495 | return 0x00000000; | ||
496 | } | ||
497 | static inline u32 sim_recv_ring_status_init_f(void) | ||
498 | { | ||
499 | return 0x0; | ||
500 | } | ||
501 | static inline u32 sim_recv_ring_status__init_v(void) | ||
502 | { | ||
503 | return 0x00000000; | ||
504 | } | ||
505 | static inline u32 sim_recv_ring_status__init_f(void) | ||
506 | { | ||
507 | return 0x0; | ||
508 | } | ||
509 | static inline u32 sim_recv_ring_status__prod_v(void) | ||
510 | { | ||
511 | return 0x00000000; | ||
512 | } | ||
513 | static inline u32 sim_recv_ring_status__prod_f(void) | ||
514 | { | ||
515 | return 0x0; | ||
516 | } | ||
517 | static inline u32 sim_recv_ring_status_invalid_v(void) | ||
518 | { | ||
519 | return 0x00000000; | ||
520 | } | ||
521 | static inline u32 sim_recv_ring_status_invalid_f(void) | ||
522 | { | ||
523 | return 0x0; | ||
524 | } | ||
525 | static inline u32 sim_recv_ring_status_valid_v(void) | ||
526 | { | ||
527 | return 0x00000001; | ||
528 | } | ||
529 | static inline u32 sim_recv_ring_status_valid_f(void) | ||
530 | { | ||
531 | return 0x8; | ||
532 | } | ||
533 | static inline u32 sim_recv_ring_size_s(void) | ||
534 | { | ||
535 | return 2; | ||
536 | } | ||
537 | static inline u32 sim_recv_ring_size_f(u32 v) | ||
538 | { | ||
539 | return (v & 0x3) << 4; | ||
540 | } | ||
541 | static inline u32 sim_recv_ring_size_m(void) | ||
542 | { | ||
543 | return 0x3 << 4; | ||
544 | } | ||
545 | static inline u32 sim_recv_ring_size_v(u32 r) | ||
546 | { | ||
547 | return (r >> 4) & 0x3; | ||
548 | } | ||
549 | static inline u32 sim_recv_ring_size_init_v(void) | ||
550 | { | ||
551 | return 0x00000000; | ||
552 | } | ||
553 | static inline u32 sim_recv_ring_size_init_f(void) | ||
554 | { | ||
555 | return 0x0; | ||
556 | } | ||
557 | static inline u32 sim_recv_ring_size__init_v(void) | ||
558 | { | ||
559 | return 0x00000000; | ||
560 | } | ||
561 | static inline u32 sim_recv_ring_size__init_f(void) | ||
562 | { | ||
563 | return 0x0; | ||
564 | } | ||
565 | static inline u32 sim_recv_ring_size__prod_v(void) | ||
566 | { | ||
567 | return 0x00000000; | ||
568 | } | ||
569 | static inline u32 sim_recv_ring_size__prod_f(void) | ||
570 | { | ||
571 | return 0x0; | ||
572 | } | ||
573 | static inline u32 sim_recv_ring_size_4kb_v(void) | ||
574 | { | ||
575 | return 0x00000000; | ||
576 | } | ||
577 | static inline u32 sim_recv_ring_size_4kb_f(void) | ||
578 | { | ||
579 | return 0x0; | ||
580 | } | ||
581 | static inline u32 sim_recv_ring_size_8kb_v(void) | ||
582 | { | ||
583 | return 0x00000001; | ||
584 | } | ||
585 | static inline u32 sim_recv_ring_size_8kb_f(void) | ||
586 | { | ||
587 | return 0x10; | ||
588 | } | ||
589 | static inline u32 sim_recv_ring_size_12kb_v(void) | ||
590 | { | ||
591 | return 0x00000002; | ||
592 | } | ||
593 | static inline u32 sim_recv_ring_size_12kb_f(void) | ||
594 | { | ||
595 | return 0x20; | ||
596 | } | ||
597 | static inline u32 sim_recv_ring_size_16kb_v(void) | ||
598 | { | ||
599 | return 0x00000003; | ||
600 | } | ||
601 | static inline u32 sim_recv_ring_size_16kb_f(void) | ||
602 | { | ||
603 | return 0x30; | ||
604 | } | ||
605 | static inline u32 sim_recv_ring_gp_in_ring_s(void) | ||
606 | { | ||
607 | return 1; | ||
608 | } | ||
609 | static inline u32 sim_recv_ring_gp_in_ring_f(u32 v) | ||
610 | { | ||
611 | return (v & 0x1) << 11; | ||
612 | } | ||
613 | static inline u32 sim_recv_ring_gp_in_ring_m(void) | ||
614 | { | ||
615 | return 0x1 << 11; | ||
616 | } | ||
617 | static inline u32 sim_recv_ring_gp_in_ring_v(u32 r) | ||
618 | { | ||
619 | return (r >> 11) & 0x1; | ||
620 | } | ||
621 | static inline u32 sim_recv_ring_gp_in_ring__init_v(void) | ||
622 | { | ||
623 | return 0x00000000; | ||
624 | } | ||
625 | static inline u32 sim_recv_ring_gp_in_ring__init_f(void) | ||
626 | { | ||
627 | return 0x0; | ||
628 | } | ||
629 | static inline u32 sim_recv_ring_gp_in_ring__prod_v(void) | ||
630 | { | ||
631 | return 0x00000000; | ||
632 | } | ||
633 | static inline u32 sim_recv_ring_gp_in_ring__prod_f(void) | ||
634 | { | ||
635 | return 0x0; | ||
636 | } | ||
637 | static inline u32 sim_recv_ring_gp_in_ring_no_v(void) | ||
638 | { | ||
639 | return 0x00000000; | ||
640 | } | ||
641 | static inline u32 sim_recv_ring_gp_in_ring_no_f(void) | ||
642 | { | ||
643 | return 0x0; | ||
644 | } | ||
645 | static inline u32 sim_recv_ring_gp_in_ring_yes_v(void) | ||
646 | { | ||
647 | return 0x00000001; | ||
648 | } | ||
649 | static inline u32 sim_recv_ring_gp_in_ring_yes_f(void) | ||
650 | { | ||
651 | return 0x800; | ||
652 | } | ||
653 | static inline u32 sim_recv_ring_addr_lo_s(void) | ||
654 | { | ||
655 | return 20; | ||
656 | } | ||
657 | static inline u32 sim_recv_ring_addr_lo_f(u32 v) | ||
658 | { | ||
659 | return (v & 0xfffff) << 12; | ||
660 | } | ||
661 | static inline u32 sim_recv_ring_addr_lo_m(void) | ||
662 | { | ||
663 | return 0xfffff << 12; | ||
664 | } | ||
665 | static inline u32 sim_recv_ring_addr_lo_v(u32 r) | ||
666 | { | ||
667 | return (r >> 12) & 0xfffff; | ||
668 | } | ||
669 | static inline u32 sim_recv_ring_addr_lo__init_v(void) | ||
670 | { | ||
671 | return 0x00000000; | ||
672 | } | ||
673 | static inline u32 sim_recv_ring_addr_lo__init_f(void) | ||
674 | { | ||
675 | return 0x0; | ||
676 | } | ||
677 | static inline u32 sim_recv_ring_addr_lo__prod_v(void) | ||
678 | { | ||
679 | return 0x00000000; | ||
680 | } | ||
681 | static inline u32 sim_recv_ring_addr_lo__prod_f(void) | ||
682 | { | ||
683 | return 0x0; | ||
684 | } | ||
685 | static inline u32 sim_recv_ring_hi_r(void) | ||
686 | { | ||
687 | return 0x00000014; | ||
688 | } | ||
689 | static inline u32 sim_recv_ring_hi_addr_s(void) | ||
690 | { | ||
691 | return 20; | ||
692 | } | ||
693 | static inline u32 sim_recv_ring_hi_addr_f(u32 v) | ||
694 | { | ||
695 | return (v & 0xfffff) << 0; | ||
696 | } | ||
697 | static inline u32 sim_recv_ring_hi_addr_m(void) | ||
698 | { | ||
699 | return 0xfffff << 0; | ||
700 | } | ||
701 | static inline u32 sim_recv_ring_hi_addr_v(u32 r) | ||
702 | { | ||
703 | return (r >> 0) & 0xfffff; | ||
704 | } | ||
705 | static inline u32 sim_recv_ring_hi_addr__init_v(void) | ||
706 | { | ||
707 | return 0x00000000; | ||
708 | } | ||
709 | static inline u32 sim_recv_ring_hi_addr__init_f(void) | ||
710 | { | ||
711 | return 0x0; | ||
712 | } | ||
713 | static inline u32 sim_recv_ring_hi_addr__prod_v(void) | ||
714 | { | ||
715 | return 0x00000000; | ||
716 | } | ||
717 | static inline u32 sim_recv_ring_hi_addr__prod_f(void) | ||
718 | { | ||
719 | return 0x0; | ||
720 | } | ||
721 | static inline u32 sim_recv_put_r(void) | ||
722 | { | ||
723 | return 0x00000018; | ||
724 | } | ||
725 | static inline u32 sim_recv_put_pointer_s(void) | ||
726 | { | ||
727 | return 11; | ||
728 | } | ||
729 | static inline u32 sim_recv_put_pointer_f(u32 v) | ||
730 | { | ||
731 | return (v & 0x7ff) << 3; | ||
732 | } | ||
733 | static inline u32 sim_recv_put_pointer_m(void) | ||
734 | { | ||
735 | return 0x7ff << 3; | ||
736 | } | ||
737 | static inline u32 sim_recv_put_pointer_v(u32 r) | ||
738 | { | ||
739 | return (r >> 3) & 0x7ff; | ||
740 | } | ||
741 | static inline u32 sim_recv_get_r(void) | ||
742 | { | ||
743 | return 0x0000001c; | ||
744 | } | ||
745 | static inline u32 sim_recv_get_pointer_s(void) | ||
746 | { | ||
747 | return 11; | ||
748 | } | ||
749 | static inline u32 sim_recv_get_pointer_f(u32 v) | ||
750 | { | ||
751 | return (v & 0x7ff) << 3; | ||
752 | } | ||
753 | static inline u32 sim_recv_get_pointer_m(void) | ||
754 | { | ||
755 | return 0x7ff << 3; | ||
756 | } | ||
757 | static inline u32 sim_recv_get_pointer_v(u32 r) | ||
758 | { | ||
759 | return (r >> 3) & 0x7ff; | ||
760 | } | ||
761 | static inline u32 sim_config_r(void) | ||
762 | { | ||
763 | return 0x00000020; | ||
764 | } | ||
765 | static inline u32 sim_config_mode_s(void) | ||
766 | { | ||
767 | return 1; | ||
768 | } | ||
769 | static inline u32 sim_config_mode_f(u32 v) | ||
770 | { | ||
771 | return (v & 0x1) << 0; | ||
772 | } | ||
773 | static inline u32 sim_config_mode_m(void) | ||
774 | { | ||
775 | return 0x1 << 0; | ||
776 | } | ||
777 | static inline u32 sim_config_mode_v(u32 r) | ||
778 | { | ||
779 | return (r >> 0) & 0x1; | ||
780 | } | ||
781 | static inline u32 sim_config_mode_disabled_v(void) | ||
782 | { | ||
783 | return 0x00000000; | ||
784 | } | ||
785 | static inline u32 sim_config_mode_disabled_f(void) | ||
786 | { | ||
787 | return 0x0; | ||
788 | } | ||
789 | static inline u32 sim_config_mode_enabled_v(void) | ||
790 | { | ||
791 | return 0x00000001; | ||
792 | } | ||
793 | static inline u32 sim_config_mode_enabled_f(void) | ||
794 | { | ||
795 | return 0x1; | ||
796 | } | ||
797 | static inline u32 sim_config_channels_s(void) | ||
798 | { | ||
799 | return 7; | ||
800 | } | ||
801 | static inline u32 sim_config_channels_f(u32 v) | ||
802 | { | ||
803 | return (v & 0x7f) << 1; | ||
804 | } | ||
805 | static inline u32 sim_config_channels_m(void) | ||
806 | { | ||
807 | return 0x7f << 1; | ||
808 | } | ||
809 | static inline u32 sim_config_channels_v(u32 r) | ||
810 | { | ||
811 | return (r >> 1) & 0x7f; | ||
812 | } | ||
813 | static inline u32 sim_config_channels_none_v(void) | ||
814 | { | ||
815 | return 0x00000000; | ||
816 | } | ||
817 | static inline u32 sim_config_channels_none_f(void) | ||
818 | { | ||
819 | return 0x0; | ||
820 | } | ||
821 | static inline u32 sim_config_cached_only_s(void) | ||
822 | { | ||
823 | return 1; | ||
824 | } | ||
825 | static inline u32 sim_config_cached_only_f(u32 v) | ||
826 | { | ||
827 | return (v & 0x1) << 8; | ||
828 | } | ||
829 | static inline u32 sim_config_cached_only_m(void) | ||
830 | { | ||
831 | return 0x1 << 8; | ||
832 | } | ||
833 | static inline u32 sim_config_cached_only_v(u32 r) | ||
834 | { | ||
835 | return (r >> 8) & 0x1; | ||
836 | } | ||
837 | static inline u32 sim_config_cached_only_disabled_v(void) | ||
838 | { | ||
839 | return 0x00000000; | ||
840 | } | ||
841 | static inline u32 sim_config_cached_only_disabled_f(void) | ||
842 | { | ||
843 | return 0x0; | ||
844 | } | ||
845 | static inline u32 sim_config_cached_only_enabled_v(void) | ||
846 | { | ||
847 | return 0x00000001; | ||
848 | } | ||
849 | static inline u32 sim_config_cached_only_enabled_f(void) | ||
850 | { | ||
851 | return 0x100; | ||
852 | } | ||
853 | static inline u32 sim_config_validity_s(void) | ||
854 | { | ||
855 | return 2; | ||
856 | } | ||
857 | static inline u32 sim_config_validity_f(u32 v) | ||
858 | { | ||
859 | return (v & 0x3) << 9; | ||
860 | } | ||
861 | static inline u32 sim_config_validity_m(void) | ||
862 | { | ||
863 | return 0x3 << 9; | ||
864 | } | ||
865 | static inline u32 sim_config_validity_v(u32 r) | ||
866 | { | ||
867 | return (r >> 9) & 0x3; | ||
868 | } | ||
869 | static inline u32 sim_config_validity__init_v(void) | ||
870 | { | ||
871 | return 0x00000001; | ||
872 | } | ||
873 | static inline u32 sim_config_validity__init_f(void) | ||
874 | { | ||
875 | return 0x200; | ||
876 | } | ||
877 | static inline u32 sim_config_validity_valid_v(void) | ||
878 | { | ||
879 | return 0x00000001; | ||
880 | } | ||
881 | static inline u32 sim_config_validity_valid_f(void) | ||
882 | { | ||
883 | return 0x200; | ||
884 | } | ||
885 | static inline u32 sim_config_simulation_s(void) | ||
886 | { | ||
887 | return 2; | ||
888 | } | ||
889 | static inline u32 sim_config_simulation_f(u32 v) | ||
890 | { | ||
891 | return (v & 0x3) << 12; | ||
892 | } | ||
893 | static inline u32 sim_config_simulation_m(void) | ||
894 | { | ||
895 | return 0x3 << 12; | ||
896 | } | ||
897 | static inline u32 sim_config_simulation_v(u32 r) | ||
898 | { | ||
899 | return (r >> 12) & 0x3; | ||
900 | } | ||
901 | static inline u32 sim_config_simulation_disabled_v(void) | ||
902 | { | ||
903 | return 0x00000000; | ||
904 | } | ||
905 | static inline u32 sim_config_simulation_disabled_f(void) | ||
906 | { | ||
907 | return 0x0; | ||
908 | } | ||
909 | static inline u32 sim_config_simulation_fmodel_v(void) | ||
910 | { | ||
911 | return 0x00000001; | ||
912 | } | ||
913 | static inline u32 sim_config_simulation_fmodel_f(void) | ||
914 | { | ||
915 | return 0x1000; | ||
916 | } | ||
917 | static inline u32 sim_config_simulation_rtlsim_v(void) | ||
918 | { | ||
919 | return 0x00000002; | ||
920 | } | ||
921 | static inline u32 sim_config_simulation_rtlsim_f(void) | ||
922 | { | ||
923 | return 0x2000; | ||
924 | } | ||
925 | static inline u32 sim_config_secondary_display_s(void) | ||
926 | { | ||
927 | return 1; | ||
928 | } | ||
929 | static inline u32 sim_config_secondary_display_f(u32 v) | ||
930 | { | ||
931 | return (v & 0x1) << 14; | ||
932 | } | ||
933 | static inline u32 sim_config_secondary_display_m(void) | ||
934 | { | ||
935 | return 0x1 << 14; | ||
936 | } | ||
937 | static inline u32 sim_config_secondary_display_v(u32 r) | ||
938 | { | ||
939 | return (r >> 14) & 0x1; | ||
940 | } | ||
941 | static inline u32 sim_config_secondary_display_disabled_v(void) | ||
942 | { | ||
943 | return 0x00000000; | ||
944 | } | ||
945 | static inline u32 sim_config_secondary_display_disabled_f(void) | ||
946 | { | ||
947 | return 0x0; | ||
948 | } | ||
949 | static inline u32 sim_config_secondary_display_enabled_v(void) | ||
950 | { | ||
951 | return 0x00000001; | ||
952 | } | ||
953 | static inline u32 sim_config_secondary_display_enabled_f(void) | ||
954 | { | ||
955 | return 0x4000; | ||
956 | } | ||
957 | static inline u32 sim_config_num_heads_s(void) | ||
958 | { | ||
959 | return 8; | ||
960 | } | ||
961 | static inline u32 sim_config_num_heads_f(u32 v) | ||
962 | { | ||
963 | return (v & 0xff) << 17; | ||
964 | } | ||
965 | static inline u32 sim_config_num_heads_m(void) | ||
966 | { | ||
967 | return 0xff << 17; | ||
968 | } | ||
969 | static inline u32 sim_config_num_heads_v(u32 r) | ||
970 | { | ||
971 | return (r >> 17) & 0xff; | ||
972 | } | ||
973 | static inline u32 sim_event_ring_r(void) | ||
974 | { | ||
975 | return 0x00000030; | ||
976 | } | ||
977 | static inline u32 sim_event_ring_target_s(void) | ||
978 | { | ||
979 | return 2; | ||
980 | } | ||
981 | static inline u32 sim_event_ring_target_f(u32 v) | ||
982 | { | ||
983 | return (v & 0x3) << 0; | ||
984 | } | ||
985 | static inline u32 sim_event_ring_target_m(void) | ||
986 | { | ||
987 | return 0x3 << 0; | ||
988 | } | ||
989 | static inline u32 sim_event_ring_target_v(u32 r) | ||
990 | { | ||
991 | return (r >> 0) & 0x3; | ||
992 | } | ||
993 | static inline u32 sim_event_ring_target_phys_init_v(void) | ||
994 | { | ||
995 | return 0x00000001; | ||
996 | } | ||
997 | static inline u32 sim_event_ring_target_phys_init_f(void) | ||
998 | { | ||
999 | return 0x1; | ||
1000 | } | ||
1001 | static inline u32 sim_event_ring_target_phys__init_v(void) | ||
1002 | { | ||
1003 | return 0x00000001; | ||
1004 | } | ||
1005 | static inline u32 sim_event_ring_target_phys__init_f(void) | ||
1006 | { | ||
1007 | return 0x1; | ||
1008 | } | ||
1009 | static inline u32 sim_event_ring_target_phys__prod_v(void) | ||
1010 | { | ||
1011 | return 0x00000001; | ||
1012 | } | ||
1013 | static inline u32 sim_event_ring_target_phys__prod_f(void) | ||
1014 | { | ||
1015 | return 0x1; | ||
1016 | } | ||
1017 | static inline u32 sim_event_ring_target_phys_nvm_v(void) | ||
1018 | { | ||
1019 | return 0x00000001; | ||
1020 | } | ||
1021 | static inline u32 sim_event_ring_target_phys_nvm_f(void) | ||
1022 | { | ||
1023 | return 0x1; | ||
1024 | } | ||
1025 | static inline u32 sim_event_ring_target_phys_pci_v(void) | ||
1026 | { | ||
1027 | return 0x00000002; | ||
1028 | } | ||
1029 | static inline u32 sim_event_ring_target_phys_pci_f(void) | ||
1030 | { | ||
1031 | return 0x2; | ||
1032 | } | ||
1033 | static inline u32 sim_event_ring_target_phys_pci_coherent_v(void) | ||
1034 | { | ||
1035 | return 0x00000003; | ||
1036 | } | ||
1037 | static inline u32 sim_event_ring_target_phys_pci_coherent_f(void) | ||
1038 | { | ||
1039 | return 0x3; | ||
1040 | } | ||
1041 | static inline u32 sim_event_ring_status_s(void) | ||
1042 | { | ||
1043 | return 1; | ||
1044 | } | ||
1045 | static inline u32 sim_event_ring_status_f(u32 v) | ||
1046 | { | ||
1047 | return (v & 0x1) << 3; | ||
1048 | } | ||
1049 | static inline u32 sim_event_ring_status_m(void) | ||
1050 | { | ||
1051 | return 0x1 << 3; | ||
1052 | } | ||
1053 | static inline u32 sim_event_ring_status_v(u32 r) | ||
1054 | { | ||
1055 | return (r >> 3) & 0x1; | ||
1056 | } | ||
1057 | static inline u32 sim_event_ring_status_init_v(void) | ||
1058 | { | ||
1059 | return 0x00000000; | ||
1060 | } | ||
1061 | static inline u32 sim_event_ring_status_init_f(void) | ||
1062 | { | ||
1063 | return 0x0; | ||
1064 | } | ||
1065 | static inline u32 sim_event_ring_status__init_v(void) | ||
1066 | { | ||
1067 | return 0x00000000; | ||
1068 | } | ||
1069 | static inline u32 sim_event_ring_status__init_f(void) | ||
1070 | { | ||
1071 | return 0x0; | ||
1072 | } | ||
1073 | static inline u32 sim_event_ring_status__prod_v(void) | ||
1074 | { | ||
1075 | return 0x00000000; | ||
1076 | } | ||
1077 | static inline u32 sim_event_ring_status__prod_f(void) | ||
1078 | { | ||
1079 | return 0x0; | ||
1080 | } | ||
1081 | static inline u32 sim_event_ring_status_invalid_v(void) | ||
1082 | { | ||
1083 | return 0x00000000; | ||
1084 | } | ||
1085 | static inline u32 sim_event_ring_status_invalid_f(void) | ||
1086 | { | ||
1087 | return 0x0; | ||
1088 | } | ||
1089 | static inline u32 sim_event_ring_status_valid_v(void) | ||
1090 | { | ||
1091 | return 0x00000001; | ||
1092 | } | ||
1093 | static inline u32 sim_event_ring_status_valid_f(void) | ||
1094 | { | ||
1095 | return 0x8; | ||
1096 | } | ||
1097 | static inline u32 sim_event_ring_size_s(void) | ||
1098 | { | ||
1099 | return 2; | ||
1100 | } | ||
1101 | static inline u32 sim_event_ring_size_f(u32 v) | ||
1102 | { | ||
1103 | return (v & 0x3) << 4; | ||
1104 | } | ||
1105 | static inline u32 sim_event_ring_size_m(void) | ||
1106 | { | ||
1107 | return 0x3 << 4; | ||
1108 | } | ||
1109 | static inline u32 sim_event_ring_size_v(u32 r) | ||
1110 | { | ||
1111 | return (r >> 4) & 0x3; | ||
1112 | } | ||
1113 | static inline u32 sim_event_ring_size_init_v(void) | ||
1114 | { | ||
1115 | return 0x00000000; | ||
1116 | } | ||
1117 | static inline u32 sim_event_ring_size_init_f(void) | ||
1118 | { | ||
1119 | return 0x0; | ||
1120 | } | ||
1121 | static inline u32 sim_event_ring_size__init_v(void) | ||
1122 | { | ||
1123 | return 0x00000000; | ||
1124 | } | ||
1125 | static inline u32 sim_event_ring_size__init_f(void) | ||
1126 | { | ||
1127 | return 0x0; | ||
1128 | } | ||
1129 | static inline u32 sim_event_ring_size__prod_v(void) | ||
1130 | { | ||
1131 | return 0x00000000; | ||
1132 | } | ||
1133 | static inline u32 sim_event_ring_size__prod_f(void) | ||
1134 | { | ||
1135 | return 0x0; | ||
1136 | } | ||
1137 | static inline u32 sim_event_ring_size_4kb_v(void) | ||
1138 | { | ||
1139 | return 0x00000000; | ||
1140 | } | ||
1141 | static inline u32 sim_event_ring_size_4kb_f(void) | ||
1142 | { | ||
1143 | return 0x0; | ||
1144 | } | ||
1145 | static inline u32 sim_event_ring_size_8kb_v(void) | ||
1146 | { | ||
1147 | return 0x00000001; | ||
1148 | } | ||
1149 | static inline u32 sim_event_ring_size_8kb_f(void) | ||
1150 | { | ||
1151 | return 0x10; | ||
1152 | } | ||
1153 | static inline u32 sim_event_ring_size_12kb_v(void) | ||
1154 | { | ||
1155 | return 0x00000002; | ||
1156 | } | ||
1157 | static inline u32 sim_event_ring_size_12kb_f(void) | ||
1158 | { | ||
1159 | return 0x20; | ||
1160 | } | ||
1161 | static inline u32 sim_event_ring_size_16kb_v(void) | ||
1162 | { | ||
1163 | return 0x00000003; | ||
1164 | } | ||
1165 | static inline u32 sim_event_ring_size_16kb_f(void) | ||
1166 | { | ||
1167 | return 0x30; | ||
1168 | } | ||
1169 | static inline u32 sim_event_ring_gp_in_ring_s(void) | ||
1170 | { | ||
1171 | return 1; | ||
1172 | } | ||
1173 | static inline u32 sim_event_ring_gp_in_ring_f(u32 v) | ||
1174 | { | ||
1175 | return (v & 0x1) << 11; | ||
1176 | } | ||
1177 | static inline u32 sim_event_ring_gp_in_ring_m(void) | ||
1178 | { | ||
1179 | return 0x1 << 11; | ||
1180 | } | ||
1181 | static inline u32 sim_event_ring_gp_in_ring_v(u32 r) | ||
1182 | { | ||
1183 | return (r >> 11) & 0x1; | ||
1184 | } | ||
1185 | static inline u32 sim_event_ring_gp_in_ring__init_v(void) | ||
1186 | { | ||
1187 | return 0x00000000; | ||
1188 | } | ||
1189 | static inline u32 sim_event_ring_gp_in_ring__init_f(void) | ||
1190 | { | ||
1191 | return 0x0; | ||
1192 | } | ||
1193 | static inline u32 sim_event_ring_gp_in_ring__prod_v(void) | ||
1194 | { | ||
1195 | return 0x00000000; | ||
1196 | } | ||
1197 | static inline u32 sim_event_ring_gp_in_ring__prod_f(void) | ||
1198 | { | ||
1199 | return 0x0; | ||
1200 | } | ||
1201 | static inline u32 sim_event_ring_gp_in_ring_no_v(void) | ||
1202 | { | ||
1203 | return 0x00000000; | ||
1204 | } | ||
1205 | static inline u32 sim_event_ring_gp_in_ring_no_f(void) | ||
1206 | { | ||
1207 | return 0x0; | ||
1208 | } | ||
1209 | static inline u32 sim_event_ring_gp_in_ring_yes_v(void) | ||
1210 | { | ||
1211 | return 0x00000001; | ||
1212 | } | ||
1213 | static inline u32 sim_event_ring_gp_in_ring_yes_f(void) | ||
1214 | { | ||
1215 | return 0x800; | ||
1216 | } | ||
1217 | static inline u32 sim_event_ring_addr_lo_s(void) | ||
1218 | { | ||
1219 | return 20; | ||
1220 | } | ||
1221 | static inline u32 sim_event_ring_addr_lo_f(u32 v) | ||
1222 | { | ||
1223 | return (v & 0xfffff) << 12; | ||
1224 | } | ||
1225 | static inline u32 sim_event_ring_addr_lo_m(void) | ||
1226 | { | ||
1227 | return 0xfffff << 12; | ||
1228 | } | ||
1229 | static inline u32 sim_event_ring_addr_lo_v(u32 r) | ||
1230 | { | ||
1231 | return (r >> 12) & 0xfffff; | ||
1232 | } | ||
1233 | static inline u32 sim_event_ring_addr_lo__init_v(void) | ||
1234 | { | ||
1235 | return 0x00000000; | ||
1236 | } | ||
1237 | static inline u32 sim_event_ring_addr_lo__init_f(void) | ||
1238 | { | ||
1239 | return 0x0; | ||
1240 | } | ||
1241 | static inline u32 sim_event_ring_addr_lo__prod_v(void) | ||
1242 | { | ||
1243 | return 0x00000000; | ||
1244 | } | ||
1245 | static inline u32 sim_event_ring_addr_lo__prod_f(void) | ||
1246 | { | ||
1247 | return 0x0; | ||
1248 | } | ||
1249 | static inline u32 sim_event_ring_hi_v(void) | ||
1250 | { | ||
1251 | return 0x00000034; | ||
1252 | } | ||
1253 | static inline u32 sim_event_ring_hi_addr_s(void) | ||
1254 | { | ||
1255 | return 20; | ||
1256 | } | ||
1257 | static inline u32 sim_event_ring_hi_addr_f(u32 v) | ||
1258 | { | ||
1259 | return (v & 0xfffff) << 0; | ||
1260 | } | ||
1261 | static inline u32 sim_event_ring_hi_addr_m(void) | ||
1262 | { | ||
1263 | return 0xfffff << 0; | ||
1264 | } | ||
1265 | static inline u32 sim_event_ring_hi_addr_v(u32 r) | ||
1266 | { | ||
1267 | return (r >> 0) & 0xfffff; | ||
1268 | } | ||
1269 | static inline u32 sim_event_ring_hi_addr__init_v(void) | ||
1270 | { | ||
1271 | return 0x00000000; | ||
1272 | } | ||
1273 | static inline u32 sim_event_ring_hi_addr__init_f(void) | ||
1274 | { | ||
1275 | return 0x0; | ||
1276 | } | ||
1277 | static inline u32 sim_event_ring_hi_addr__prod_v(void) | ||
1278 | { | ||
1279 | return 0x00000000; | ||
1280 | } | ||
1281 | static inline u32 sim_event_ring_hi_addr__prod_f(void) | ||
1282 | { | ||
1283 | return 0x0; | ||
1284 | } | ||
1285 | static inline u32 sim_event_put_r(void) | ||
1286 | { | ||
1287 | return 0x00000038; | ||
1288 | } | ||
1289 | static inline u32 sim_event_put_pointer_s(void) | ||
1290 | { | ||
1291 | return 30; | ||
1292 | } | ||
1293 | static inline u32 sim_event_put_pointer_f(u32 v) | ||
1294 | { | ||
1295 | return (v & 0x3fffffff) << 2; | ||
1296 | } | ||
1297 | static inline u32 sim_event_put_pointer_m(void) | ||
1298 | { | ||
1299 | return 0x3fffffff << 2; | ||
1300 | } | ||
1301 | static inline u32 sim_event_put_pointer_v(u32 r) | ||
1302 | { | ||
1303 | return (r >> 2) & 0x3fffffff; | ||
1304 | } | ||
1305 | static inline u32 sim_event_get_r(void) | ||
1306 | { | ||
1307 | return 0x0000003c; | ||
1308 | } | ||
1309 | static inline u32 sim_event_get_pointer_s(void) | ||
1310 | { | ||
1311 | return 30; | ||
1312 | } | ||
1313 | static inline u32 sim_event_get_pointer_f(u32 v) | ||
1314 | { | ||
1315 | return (v & 0x3fffffff) << 2; | ||
1316 | } | ||
1317 | static inline u32 sim_event_get_pointer_m(void) | ||
1318 | { | ||
1319 | return 0x3fffffff << 2; | ||
1320 | } | ||
1321 | static inline u32 sim_event_get_pointer_v(u32 r) | ||
1322 | { | ||
1323 | return (r >> 2) & 0x3fffffff; | ||
1324 | } | ||
1325 | static inline u32 sim_status_r(void) | ||
1326 | { | ||
1327 | return 0x00000028; | ||
1328 | } | ||
1329 | static inline u32 sim_status_send_put_s(void) | ||
1330 | { | ||
1331 | return 1; | ||
1332 | } | ||
1333 | static inline u32 sim_status_send_put_f(u32 v) | ||
1334 | { | ||
1335 | return (v & 0x1) << 0; | ||
1336 | } | ||
1337 | static inline u32 sim_status_send_put_m(void) | ||
1338 | { | ||
1339 | return 0x1 << 0; | ||
1340 | } | ||
1341 | static inline u32 sim_status_send_put_v(u32 r) | ||
1342 | { | ||
1343 | return (r >> 0) & 0x1; | ||
1344 | } | ||
1345 | static inline u32 sim_status_send_put__init_v(void) | ||
1346 | { | ||
1347 | return 0x00000000; | ||
1348 | } | ||
1349 | static inline u32 sim_status_send_put__init_f(void) | ||
1350 | { | ||
1351 | return 0x0; | ||
1352 | } | ||
1353 | static inline u32 sim_status_send_put_idle_v(void) | ||
1354 | { | ||
1355 | return 0x00000000; | ||
1356 | } | ||
1357 | static inline u32 sim_status_send_put_idle_f(void) | ||
1358 | { | ||
1359 | return 0x0; | ||
1360 | } | ||
1361 | static inline u32 sim_status_send_put_pending_v(void) | ||
1362 | { | ||
1363 | return 0x00000001; | ||
1364 | } | ||
1365 | static inline u32 sim_status_send_put_pending_f(void) | ||
1366 | { | ||
1367 | return 0x1; | ||
1368 | } | ||
1369 | static inline u32 sim_status_send_get_s(void) | ||
1370 | { | ||
1371 | return 1; | ||
1372 | } | ||
1373 | static inline u32 sim_status_send_get_f(u32 v) | ||
1374 | { | ||
1375 | return (v & 0x1) << 1; | ||
1376 | } | ||
1377 | static inline u32 sim_status_send_get_m(void) | ||
1378 | { | ||
1379 | return 0x1 << 1; | ||
1380 | } | ||
1381 | static inline u32 sim_status_send_get_v(u32 r) | ||
1382 | { | ||
1383 | return (r >> 1) & 0x1; | ||
1384 | } | ||
1385 | static inline u32 sim_status_send_get__init_v(void) | ||
1386 | { | ||
1387 | return 0x00000000; | ||
1388 | } | ||
1389 | static inline u32 sim_status_send_get__init_f(void) | ||
1390 | { | ||
1391 | return 0x0; | ||
1392 | } | ||
1393 | static inline u32 sim_status_send_get_idle_v(void) | ||
1394 | { | ||
1395 | return 0x00000000; | ||
1396 | } | ||
1397 | static inline u32 sim_status_send_get_idle_f(void) | ||
1398 | { | ||
1399 | return 0x0; | ||
1400 | } | ||
1401 | static inline u32 sim_status_send_get_pending_v(void) | ||
1402 | { | ||
1403 | return 0x00000001; | ||
1404 | } | ||
1405 | static inline u32 sim_status_send_get_pending_f(void) | ||
1406 | { | ||
1407 | return 0x2; | ||
1408 | } | ||
1409 | static inline u32 sim_status_send_get_clear_v(void) | ||
1410 | { | ||
1411 | return 0x00000001; | ||
1412 | } | ||
1413 | static inline u32 sim_status_send_get_clear_f(void) | ||
1414 | { | ||
1415 | return 0x2; | ||
1416 | } | ||
1417 | static inline u32 sim_status_recv_put_s(void) | ||
1418 | { | ||
1419 | return 1; | ||
1420 | } | ||
1421 | static inline u32 sim_status_recv_put_f(u32 v) | ||
1422 | { | ||
1423 | return (v & 0x1) << 2; | ||
1424 | } | ||
1425 | static inline u32 sim_status_recv_put_m(void) | ||
1426 | { | ||
1427 | return 0x1 << 2; | ||
1428 | } | ||
1429 | static inline u32 sim_status_recv_put_v(u32 r) | ||
1430 | { | ||
1431 | return (r >> 2) & 0x1; | ||
1432 | } | ||
1433 | static inline u32 sim_status_recv_put__init_v(void) | ||
1434 | { | ||
1435 | return 0x00000000; | ||
1436 | } | ||
1437 | static inline u32 sim_status_recv_put__init_f(void) | ||
1438 | { | ||
1439 | return 0x0; | ||
1440 | } | ||
1441 | static inline u32 sim_status_recv_put_idle_v(void) | ||
1442 | { | ||
1443 | return 0x00000000; | ||
1444 | } | ||
1445 | static inline u32 sim_status_recv_put_idle_f(void) | ||
1446 | { | ||
1447 | return 0x0; | ||
1448 | } | ||
1449 | static inline u32 sim_status_recv_put_pending_v(void) | ||
1450 | { | ||
1451 | return 0x00000001; | ||
1452 | } | ||
1453 | static inline u32 sim_status_recv_put_pending_f(void) | ||
1454 | { | ||
1455 | return 0x4; | ||
1456 | } | ||
1457 | static inline u32 sim_status_recv_put_clear_v(void) | ||
1458 | { | ||
1459 | return 0x00000001; | ||
1460 | } | ||
1461 | static inline u32 sim_status_recv_put_clear_f(void) | ||
1462 | { | ||
1463 | return 0x4; | ||
1464 | } | ||
1465 | static inline u32 sim_status_recv_get_s(void) | ||
1466 | { | ||
1467 | return 1; | ||
1468 | } | ||
1469 | static inline u32 sim_status_recv_get_f(u32 v) | ||
1470 | { | ||
1471 | return (v & 0x1) << 3; | ||
1472 | } | ||
1473 | static inline u32 sim_status_recv_get_m(void) | ||
1474 | { | ||
1475 | return 0x1 << 3; | ||
1476 | } | ||
1477 | static inline u32 sim_status_recv_get_v(u32 r) | ||
1478 | { | ||
1479 | return (r >> 3) & 0x1; | ||
1480 | } | ||
1481 | static inline u32 sim_status_recv_get__init_v(void) | ||
1482 | { | ||
1483 | return 0x00000000; | ||
1484 | } | ||
1485 | static inline u32 sim_status_recv_get__init_f(void) | ||
1486 | { | ||
1487 | return 0x0; | ||
1488 | } | ||
1489 | static inline u32 sim_status_recv_get_idle_v(void) | ||
1490 | { | ||
1491 | return 0x00000000; | ||
1492 | } | ||
1493 | static inline u32 sim_status_recv_get_idle_f(void) | ||
1494 | { | ||
1495 | return 0x0; | ||
1496 | } | ||
1497 | static inline u32 sim_status_recv_get_pending_v(void) | ||
1498 | { | ||
1499 | return 0x00000001; | ||
1500 | } | ||
1501 | static inline u32 sim_status_recv_get_pending_f(void) | ||
1502 | { | ||
1503 | return 0x8; | ||
1504 | } | ||
1505 | static inline u32 sim_status_event_put_s(void) | ||
1506 | { | ||
1507 | return 1; | ||
1508 | } | ||
1509 | static inline u32 sim_status_event_put_f(u32 v) | ||
1510 | { | ||
1511 | return (v & 0x1) << 4; | ||
1512 | } | ||
1513 | static inline u32 sim_status_event_put_m(void) | ||
1514 | { | ||
1515 | return 0x1 << 4; | ||
1516 | } | ||
1517 | static inline u32 sim_status_event_put_v(u32 r) | ||
1518 | { | ||
1519 | return (r >> 4) & 0x1; | ||
1520 | } | ||
1521 | static inline u32 sim_status_event_put__init_v(void) | ||
1522 | { | ||
1523 | return 0x00000000; | ||
1524 | } | ||
1525 | static inline u32 sim_status_event_put__init_f(void) | ||
1526 | { | ||
1527 | return 0x0; | ||
1528 | } | ||
1529 | static inline u32 sim_status_event_put_idle_v(void) | ||
1530 | { | ||
1531 | return 0x00000000; | ||
1532 | } | ||
1533 | static inline u32 sim_status_event_put_idle_f(void) | ||
1534 | { | ||
1535 | return 0x0; | ||
1536 | } | ||
1537 | static inline u32 sim_status_event_put_pending_v(void) | ||
1538 | { | ||
1539 | return 0x00000001; | ||
1540 | } | ||
1541 | static inline u32 sim_status_event_put_pending_f(void) | ||
1542 | { | ||
1543 | return 0x10; | ||
1544 | } | ||
1545 | static inline u32 sim_status_event_put_clear_v(void) | ||
1546 | { | ||
1547 | return 0x00000001; | ||
1548 | } | ||
1549 | static inline u32 sim_status_event_put_clear_f(void) | ||
1550 | { | ||
1551 | return 0x10; | ||
1552 | } | ||
1553 | static inline u32 sim_status_event_get_s(void) | ||
1554 | { | ||
1555 | return 1; | ||
1556 | } | ||
1557 | static inline u32 sim_status_event_get_f(u32 v) | ||
1558 | { | ||
1559 | return (v & 0x1) << 5; | ||
1560 | } | ||
1561 | static inline u32 sim_status_event_get_m(void) | ||
1562 | { | ||
1563 | return 0x1 << 5; | ||
1564 | } | ||
1565 | static inline u32 sim_status_event_get_v(u32 r) | ||
1566 | { | ||
1567 | return (r >> 5) & 0x1; | ||
1568 | } | ||
1569 | static inline u32 sim_status_event_get__init_v(void) | ||
1570 | { | ||
1571 | return 0x00000000; | ||
1572 | } | ||
1573 | static inline u32 sim_status_event_get__init_f(void) | ||
1574 | { | ||
1575 | return 0x0; | ||
1576 | } | ||
1577 | static inline u32 sim_status_event_get_idle_v(void) | ||
1578 | { | ||
1579 | return 0x00000000; | ||
1580 | } | ||
1581 | static inline u32 sim_status_event_get_idle_f(void) | ||
1582 | { | ||
1583 | return 0x0; | ||
1584 | } | ||
1585 | static inline u32 sim_status_event_get_pending_v(void) | ||
1586 | { | ||
1587 | return 0x00000001; | ||
1588 | } | ||
1589 | static inline u32 sim_status_event_get_pending_f(void) | ||
1590 | { | ||
1591 | return 0x20; | ||
1592 | } | ||
1593 | static inline u32 sim_control_r(void) | ||
1594 | { | ||
1595 | return 0x0000002c; | ||
1596 | } | ||
1597 | static inline u32 sim_control_send_put_s(void) | ||
1598 | { | ||
1599 | return 1; | ||
1600 | } | ||
1601 | static inline u32 sim_control_send_put_f(u32 v) | ||
1602 | { | ||
1603 | return (v & 0x1) << 0; | ||
1604 | } | ||
1605 | static inline u32 sim_control_send_put_m(void) | ||
1606 | { | ||
1607 | return 0x1 << 0; | ||
1608 | } | ||
1609 | static inline u32 sim_control_send_put_v(u32 r) | ||
1610 | { | ||
1611 | return (r >> 0) & 0x1; | ||
1612 | } | ||
1613 | static inline u32 sim_control_send_put__init_v(void) | ||
1614 | { | ||
1615 | return 0x00000000; | ||
1616 | } | ||
1617 | static inline u32 sim_control_send_put__init_f(void) | ||
1618 | { | ||
1619 | return 0x0; | ||
1620 | } | ||
1621 | static inline u32 sim_control_send_put_disabled_v(void) | ||
1622 | { | ||
1623 | return 0x00000000; | ||
1624 | } | ||
1625 | static inline u32 sim_control_send_put_disabled_f(void) | ||
1626 | { | ||
1627 | return 0x0; | ||
1628 | } | ||
1629 | static inline u32 sim_control_send_put_enabled_v(void) | ||
1630 | { | ||
1631 | return 0x00000001; | ||
1632 | } | ||
1633 | static inline u32 sim_control_send_put_enabled_f(void) | ||
1634 | { | ||
1635 | return 0x1; | ||
1636 | } | ||
1637 | static inline u32 sim_control_send_get_s(void) | ||
1638 | { | ||
1639 | return 1; | ||
1640 | } | ||
1641 | static inline u32 sim_control_send_get_f(u32 v) | ||
1642 | { | ||
1643 | return (v & 0x1) << 1; | ||
1644 | } | ||
1645 | static inline u32 sim_control_send_get_m(void) | ||
1646 | { | ||
1647 | return 0x1 << 1; | ||
1648 | } | ||
1649 | static inline u32 sim_control_send_get_v(u32 r) | ||
1650 | { | ||
1651 | return (r >> 1) & 0x1; | ||
1652 | } | ||
1653 | static inline u32 sim_control_send_get__init_v(void) | ||
1654 | { | ||
1655 | return 0x00000000; | ||
1656 | } | ||
1657 | static inline u32 sim_control_send_get__init_f(void) | ||
1658 | { | ||
1659 | return 0x0; | ||
1660 | } | ||
1661 | static inline u32 sim_control_send_get_disabled_v(void) | ||
1662 | { | ||
1663 | return 0x00000000; | ||
1664 | } | ||
1665 | static inline u32 sim_control_send_get_disabled_f(void) | ||
1666 | { | ||
1667 | return 0x0; | ||
1668 | } | ||
1669 | static inline u32 sim_control_send_get_enabled_v(void) | ||
1670 | { | ||
1671 | return 0x00000001; | ||
1672 | } | ||
1673 | static inline u32 sim_control_send_get_enabled_f(void) | ||
1674 | { | ||
1675 | return 0x2; | ||
1676 | } | ||
1677 | static inline u32 sim_control_recv_put_s(void) | ||
1678 | { | ||
1679 | return 1; | ||
1680 | } | ||
1681 | static inline u32 sim_control_recv_put_f(u32 v) | ||
1682 | { | ||
1683 | return (v & 0x1) << 2; | ||
1684 | } | ||
1685 | static inline u32 sim_control_recv_put_m(void) | ||
1686 | { | ||
1687 | return 0x1 << 2; | ||
1688 | } | ||
1689 | static inline u32 sim_control_recv_put_v(u32 r) | ||
1690 | { | ||
1691 | return (r >> 2) & 0x1; | ||
1692 | } | ||
1693 | static inline u32 sim_control_recv_put__init_v(void) | ||
1694 | { | ||
1695 | return 0x00000000; | ||
1696 | } | ||
1697 | static inline u32 sim_control_recv_put__init_f(void) | ||
1698 | { | ||
1699 | return 0x0; | ||
1700 | } | ||
1701 | static inline u32 sim_control_recv_put_disabled_v(void) | ||
1702 | { | ||
1703 | return 0x00000000; | ||
1704 | } | ||
1705 | static inline u32 sim_control_recv_put_disabled_f(void) | ||
1706 | { | ||
1707 | return 0x0; | ||
1708 | } | ||
1709 | static inline u32 sim_control_recv_put_enabled_v(void) | ||
1710 | { | ||
1711 | return 0x00000001; | ||
1712 | } | ||
1713 | static inline u32 sim_control_recv_put_enabled_f(void) | ||
1714 | { | ||
1715 | return 0x4; | ||
1716 | } | ||
1717 | static inline u32 sim_control_recv_get_s(void) | ||
1718 | { | ||
1719 | return 1; | ||
1720 | } | ||
1721 | static inline u32 sim_control_recv_get_f(u32 v) | ||
1722 | { | ||
1723 | return (v & 0x1) << 3; | ||
1724 | } | ||
1725 | static inline u32 sim_control_recv_get_m(void) | ||
1726 | { | ||
1727 | return 0x1 << 3; | ||
1728 | } | ||
1729 | static inline u32 sim_control_recv_get_v(u32 r) | ||
1730 | { | ||
1731 | return (r >> 3) & 0x1; | ||
1732 | } | ||
1733 | static inline u32 sim_control_recv_get__init_v(void) | ||
1734 | { | ||
1735 | return 0x00000000; | ||
1736 | } | ||
1737 | static inline u32 sim_control_recv_get__init_f(void) | ||
1738 | { | ||
1739 | return 0x0; | ||
1740 | } | ||
1741 | static inline u32 sim_control_recv_get_disabled_v(void) | ||
1742 | { | ||
1743 | return 0x00000000; | ||
1744 | } | ||
1745 | static inline u32 sim_control_recv_get_disabled_f(void) | ||
1746 | { | ||
1747 | return 0x0; | ||
1748 | } | ||
1749 | static inline u32 sim_control_recv_get_enabled_v(void) | ||
1750 | { | ||
1751 | return 0x00000001; | ||
1752 | } | ||
1753 | static inline u32 sim_control_recv_get_enabled_f(void) | ||
1754 | { | ||
1755 | return 0x8; | ||
1756 | } | ||
1757 | static inline u32 sim_control_event_put_s(void) | ||
1758 | { | ||
1759 | return 1; | ||
1760 | } | ||
1761 | static inline u32 sim_control_event_put_f(u32 v) | ||
1762 | { | ||
1763 | return (v & 0x1) << 4; | ||
1764 | } | ||
1765 | static inline u32 sim_control_event_put_m(void) | ||
1766 | { | ||
1767 | return 0x1 << 4; | ||
1768 | } | ||
1769 | static inline u32 sim_control_event_put_v(u32 r) | ||
1770 | { | ||
1771 | return (r >> 4) & 0x1; | ||
1772 | } | ||
1773 | static inline u32 sim_control_event_put__init_v(void) | ||
1774 | { | ||
1775 | return 0x00000000; | ||
1776 | } | ||
1777 | static inline u32 sim_control_event_put__init_f(void) | ||
1778 | { | ||
1779 | return 0x0; | ||
1780 | } | ||
1781 | static inline u32 sim_control_event_put_disabled_v(void) | ||
1782 | { | ||
1783 | return 0x00000000; | ||
1784 | } | ||
1785 | static inline u32 sim_control_event_put_disabled_f(void) | ||
1786 | { | ||
1787 | return 0x0; | ||
1788 | } | ||
1789 | static inline u32 sim_control_event_put_enabled_v(void) | ||
1790 | { | ||
1791 | return 0x00000001; | ||
1792 | } | ||
1793 | static inline u32 sim_control_event_put_enabled_f(void) | ||
1794 | { | ||
1795 | return 0x10; | ||
1796 | } | ||
1797 | static inline u32 sim_control_event_get_s(void) | ||
1798 | { | ||
1799 | return 1; | ||
1800 | } | ||
1801 | static inline u32 sim_control_event_get_f(u32 v) | ||
1802 | { | ||
1803 | return (v & 0x1) << 5; | ||
1804 | } | ||
1805 | static inline u32 sim_control_event_get_m(void) | ||
1806 | { | ||
1807 | return 0x1 << 5; | ||
1808 | } | ||
1809 | static inline u32 sim_control_event_get_v(u32 r) | ||
1810 | { | ||
1811 | return (r >> 5) & 0x1; | ||
1812 | } | ||
1813 | static inline u32 sim_control_event_get__init_v(void) | ||
1814 | { | ||
1815 | return 0x00000000; | ||
1816 | } | ||
1817 | static inline u32 sim_control_event_get__init_f(void) | ||
1818 | { | ||
1819 | return 0x0; | ||
1820 | } | ||
1821 | static inline u32 sim_control_event_get_disabled_v(void) | ||
1822 | { | ||
1823 | return 0x00000000; | ||
1824 | } | ||
1825 | static inline u32 sim_control_event_get_disabled_f(void) | ||
1826 | { | ||
1827 | return 0x0; | ||
1828 | } | ||
1829 | static inline u32 sim_control_event_get_enabled_v(void) | ||
1830 | { | ||
1831 | return 0x00000001; | ||
1832 | } | ||
1833 | static inline u32 sim_control_event_get_enabled_f(void) | ||
1834 | { | ||
1835 | return 0x20; | ||
1836 | } | ||
1837 | static inline u32 sim_dma_r(void) | ||
1838 | { | ||
1839 | return 0x00000000; | ||
1840 | } | ||
1841 | static inline u32 sim_dma_target_s(void) | ||
1842 | { | ||
1843 | return 2; | ||
1844 | } | ||
1845 | static inline u32 sim_dma_target_f(u32 v) | ||
1846 | { | ||
1847 | return (v & 0x3) << 0; | ||
1848 | } | ||
1849 | static inline u32 sim_dma_target_m(void) | ||
1850 | { | ||
1851 | return 0x3 << 0; | ||
1852 | } | ||
1853 | static inline u32 sim_dma_target_v(u32 r) | ||
1854 | { | ||
1855 | return (r >> 0) & 0x3; | ||
1856 | } | ||
1857 | static inline u32 sim_dma_target_phys_init_v(void) | ||
1858 | { | ||
1859 | return 0x00000001; | ||
1860 | } | ||
1861 | static inline u32 sim_dma_target_phys_init_f(void) | ||
1862 | { | ||
1863 | return 0x1; | ||
1864 | } | ||
1865 | static inline u32 sim_dma_target_phys__init_v(void) | ||
1866 | { | ||
1867 | return 0x00000001; | ||
1868 | } | ||
1869 | static inline u32 sim_dma_target_phys__init_f(void) | ||
1870 | { | ||
1871 | return 0x1; | ||
1872 | } | ||
1873 | static inline u32 sim_dma_target_phys__prod_v(void) | ||
1874 | { | ||
1875 | return 0x00000001; | ||
1876 | } | ||
1877 | static inline u32 sim_dma_target_phys__prod_f(void) | ||
1878 | { | ||
1879 | return 0x1; | ||
1880 | } | ||
1881 | static inline u32 sim_dma_target_phys_nvm_v(void) | ||
1882 | { | ||
1883 | return 0x00000001; | ||
1884 | } | ||
1885 | static inline u32 sim_dma_target_phys_nvm_f(void) | ||
1886 | { | ||
1887 | return 0x1; | ||
1888 | } | ||
1889 | static inline u32 sim_dma_target_phys_pci_v(void) | ||
1890 | { | ||
1891 | return 0x00000002; | ||
1892 | } | ||
1893 | static inline u32 sim_dma_target_phys_pci_f(void) | ||
1894 | { | ||
1895 | return 0x2; | ||
1896 | } | ||
1897 | static inline u32 sim_dma_target_phys_pci_coherent_v(void) | ||
1898 | { | ||
1899 | return 0x00000003; | ||
1900 | } | ||
1901 | static inline u32 sim_dma_target_phys_pci_coherent_f(void) | ||
1902 | { | ||
1903 | return 0x3; | ||
1904 | } | ||
1905 | static inline u32 sim_dma_status_s(void) | ||
1906 | { | ||
1907 | return 1; | ||
1908 | } | ||
1909 | static inline u32 sim_dma_status_f(u32 v) | ||
1910 | { | ||
1911 | return (v & 0x1) << 3; | ||
1912 | } | ||
1913 | static inline u32 sim_dma_status_m(void) | ||
1914 | { | ||
1915 | return 0x1 << 3; | ||
1916 | } | ||
1917 | static inline u32 sim_dma_status_v(u32 r) | ||
1918 | { | ||
1919 | return (r >> 3) & 0x1; | ||
1920 | } | ||
1921 | static inline u32 sim_dma_status_init_v(void) | ||
1922 | { | ||
1923 | return 0x00000000; | ||
1924 | } | ||
1925 | static inline u32 sim_dma_status_init_f(void) | ||
1926 | { | ||
1927 | return 0x0; | ||
1928 | } | ||
1929 | static inline u32 sim_dma_status__init_v(void) | ||
1930 | { | ||
1931 | return 0x00000000; | ||
1932 | } | ||
1933 | static inline u32 sim_dma_status__init_f(void) | ||
1934 | { | ||
1935 | return 0x0; | ||
1936 | } | ||
1937 | static inline u32 sim_dma_status__prod_v(void) | ||
1938 | { | ||
1939 | return 0x00000000; | ||
1940 | } | ||
1941 | static inline u32 sim_dma_status__prod_f(void) | ||
1942 | { | ||
1943 | return 0x0; | ||
1944 | } | ||
1945 | static inline u32 sim_dma_status_invalid_v(void) | ||
1946 | { | ||
1947 | return 0x00000000; | ||
1948 | } | ||
1949 | static inline u32 sim_dma_status_invalid_f(void) | ||
1950 | { | ||
1951 | return 0x0; | ||
1952 | } | ||
1953 | static inline u32 sim_dma_status_valid_v(void) | ||
1954 | { | ||
1955 | return 0x00000001; | ||
1956 | } | ||
1957 | static inline u32 sim_dma_status_valid_f(void) | ||
1958 | { | ||
1959 | return 0x8; | ||
1960 | } | ||
1961 | static inline u32 sim_dma_size_s(void) | ||
1962 | { | ||
1963 | return 2; | ||
1964 | } | ||
1965 | static inline u32 sim_dma_size_f(u32 v) | ||
1966 | { | ||
1967 | return (v & 0x3) << 4; | ||
1968 | } | ||
1969 | static inline u32 sim_dma_size_m(void) | ||
1970 | { | ||
1971 | return 0x3 << 4; | ||
1972 | } | ||
1973 | static inline u32 sim_dma_size_v(u32 r) | ||
1974 | { | ||
1975 | return (r >> 4) & 0x3; | ||
1976 | } | ||
1977 | static inline u32 sim_dma_size_init_v(void) | ||
1978 | { | ||
1979 | return 0x00000000; | ||
1980 | } | ||
1981 | static inline u32 sim_dma_size_init_f(void) | ||
1982 | { | ||
1983 | return 0x0; | ||
1984 | } | ||
1985 | static inline u32 sim_dma_size__init_v(void) | ||
1986 | { | ||
1987 | return 0x00000000; | ||
1988 | } | ||
1989 | static inline u32 sim_dma_size__init_f(void) | ||
1990 | { | ||
1991 | return 0x0; | ||
1992 | } | ||
1993 | static inline u32 sim_dma_size__prod_v(void) | ||
1994 | { | ||
1995 | return 0x00000000; | ||
1996 | } | ||
1997 | static inline u32 sim_dma_size__prod_f(void) | ||
1998 | { | ||
1999 | return 0x0; | ||
2000 | } | ||
2001 | static inline u32 sim_dma_size_4kb_v(void) | ||
2002 | { | ||
2003 | return 0x00000000; | ||
2004 | } | ||
2005 | static inline u32 sim_dma_size_4kb_f(void) | ||
2006 | { | ||
2007 | return 0x0; | ||
2008 | } | ||
2009 | static inline u32 sim_dma_size_8kb_v(void) | ||
2010 | { | ||
2011 | return 0x00000001; | ||
2012 | } | ||
2013 | static inline u32 sim_dma_size_8kb_f(void) | ||
2014 | { | ||
2015 | return 0x10; | ||
2016 | } | ||
2017 | static inline u32 sim_dma_size_12kb_v(void) | ||
2018 | { | ||
2019 | return 0x00000002; | ||
2020 | } | ||
2021 | static inline u32 sim_dma_size_12kb_f(void) | ||
2022 | { | ||
2023 | return 0x20; | ||
2024 | } | ||
2025 | static inline u32 sim_dma_size_16kb_v(void) | ||
2026 | { | ||
2027 | return 0x00000003; | ||
2028 | } | ||
2029 | static inline u32 sim_dma_size_16kb_f(void) | ||
2030 | { | ||
2031 | return 0x30; | ||
2032 | } | ||
2033 | static inline u32 sim_dma_addr_lo_s(void) | ||
2034 | { | ||
2035 | return 20; | ||
2036 | } | ||
2037 | static inline u32 sim_dma_addr_lo_f(u32 v) | ||
2038 | { | ||
2039 | return (v & 0xfffff) << 12; | ||
2040 | } | ||
2041 | static inline u32 sim_dma_addr_lo_m(void) | ||
2042 | { | ||
2043 | return 0xfffff << 12; | ||
2044 | } | ||
2045 | static inline u32 sim_dma_addr_lo_v(u32 r) | ||
2046 | { | ||
2047 | return (r >> 12) & 0xfffff; | ||
2048 | } | ||
2049 | static inline u32 sim_dma_addr_lo__init_v(void) | ||
2050 | { | ||
2051 | return 0x00000000; | ||
2052 | } | ||
2053 | static inline u32 sim_dma_addr_lo__init_f(void) | ||
2054 | { | ||
2055 | return 0x0; | ||
2056 | } | ||
2057 | static inline u32 sim_dma_addr_lo__prod_v(void) | ||
2058 | { | ||
2059 | return 0x00000000; | ||
2060 | } | ||
2061 | static inline u32 sim_dma_addr_lo__prod_f(void) | ||
2062 | { | ||
2063 | return 0x0; | ||
2064 | } | ||
2065 | static inline u32 sim_dma_hi_r(void) | ||
2066 | { | ||
2067 | return 0x00000004; | ||
2068 | } | ||
2069 | static inline u32 sim_dma_hi_addr_s(void) | ||
2070 | { | ||
2071 | return 20; | ||
2072 | } | ||
2073 | static inline u32 sim_dma_hi_addr_f(u32 v) | ||
2074 | { | ||
2075 | return (v & 0xfffff) << 0; | ||
2076 | } | ||
2077 | static inline u32 sim_dma_hi_addr_m(void) | ||
2078 | { | ||
2079 | return 0xfffff << 0; | ||
2080 | } | ||
2081 | static inline u32 sim_dma_hi_addr_v(u32 r) | ||
2082 | { | ||
2083 | return (r >> 0) & 0xfffff; | ||
2084 | } | ||
2085 | static inline u32 sim_dma_hi_addr__init_v(void) | ||
2086 | { | ||
2087 | return 0x00000000; | ||
2088 | } | ||
2089 | static inline u32 sim_dma_hi_addr__init_f(void) | ||
2090 | { | ||
2091 | return 0x0; | ||
2092 | } | ||
2093 | static inline u32 sim_dma_hi_addr__prod_v(void) | ||
2094 | { | ||
2095 | return 0x00000000; | ||
2096 | } | ||
2097 | static inline u32 sim_dma_hi_addr__prod_f(void) | ||
2098 | { | ||
2099 | return 0x0; | ||
2100 | } | ||
2101 | static inline u32 sim_msg_signature_r(void) | ||
2102 | { | ||
2103 | return 0x00000000; | ||
2104 | } | ||
2105 | static inline u32 sim_msg_signature_valid_v(void) | ||
2106 | { | ||
2107 | return 0x43505256; | ||
2108 | } | ||
2109 | static inline u32 sim_msg_length_r(void) | ||
2110 | { | ||
2111 | return 0x00000004; | ||
2112 | } | ||
2113 | static inline u32 sim_msg_function_r(void) | ||
2114 | { | ||
2115 | return 0x00000008; | ||
2116 | } | ||
2117 | static inline u32 sim_msg_function_sim_escape_read_v(void) | ||
2118 | { | ||
2119 | return 0x00000023; | ||
2120 | } | ||
2121 | static inline u32 sim_msg_function_sim_escape_write_v(void) | ||
2122 | { | ||
2123 | return 0x00000024; | ||
2124 | } | ||
2125 | static inline u32 sim_msg_result_r(void) | ||
2126 | { | ||
2127 | return 0x0000000c; | ||
2128 | } | ||
2129 | static inline u32 sim_msg_result_success_v(void) | ||
2130 | { | ||
2131 | return 0x00000000; | ||
2132 | } | ||
2133 | static inline u32 sim_msg_result_rpc_pending_v(void) | ||
2134 | { | ||
2135 | return 0xFFFFFFFF; | ||
2136 | } | ||
2137 | static inline u32 sim_msg_sequence_r(void) | ||
2138 | { | ||
2139 | return 0x00000010; | ||
2140 | } | ||
2141 | static inline u32 sim_msg_spare_r(void) | ||
2142 | { | ||
2143 | return 0x00000014; | ||
2144 | } | ||
2145 | static inline u32 sim_msg_spare__init_v(void) | ||
2146 | { | ||
2147 | return 0x00000000; | ||
2148 | } | ||
2149 | |||
2150 | #endif /* __hw_sim_gk20a_h__ */ | ||