diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2014-10-27 03:16:51 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:52 -0400 |
commit | 4739499f07b29282ee1031d08adaa76c238da2a6 (patch) | |
tree | 10caa152eea6250e46cad6172553069b4bb3dcb9 /drivers/gpu/nvgpu/gk20a/hw_pwr_gk20a.h | |
parent | b5bb4f53dbdde8473e1160d4522c5d9da55f115f (diff) |
gpu: nvgpu: Sync gk20a and gm20b headers
Synchronize gk20a and gm20b headers. All registers which were added
to gk20a are now added to gm20b, and some registers that are unused
are removed.
Bug 1567274
Change-Id: Ia3b7958c148e495cbff420ee56bb448db0f58680
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590313
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/hw_pwr_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_pwr_gk20a.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/hw_pwr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_pwr_gk20a.h index d7d26b80..35312bd4 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_pwr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_pwr_gk20a.h | |||
@@ -290,6 +290,42 @@ static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) | |||
290 | { | 290 | { |
291 | return (v & 0x1) << 1; | 291 | return (v & 0x1) << 1; |
292 | } | 292 | } |
293 | static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) | ||
294 | { | ||
295 | return (v & 0x1) << 4; | ||
296 | } | ||
297 | static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) | ||
298 | { | ||
299 | return 0x1 << 4; | ||
300 | } | ||
301 | static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) | ||
302 | { | ||
303 | return (r >> 4) & 0x1; | ||
304 | } | ||
305 | static inline u32 pwr_falcon_imemc_r(u32 i) | ||
306 | { | ||
307 | return 0x0010a180 + i*16; | ||
308 | } | ||
309 | static inline u32 pwr_falcon_imemc_offs_f(u32 v) | ||
310 | { | ||
311 | return (v & 0x3f) << 2; | ||
312 | } | ||
313 | static inline u32 pwr_falcon_imemc_blk_f(u32 v) | ||
314 | { | ||
315 | return (v & 0xff) << 8; | ||
316 | } | ||
317 | static inline u32 pwr_falcon_imemc_aincw_f(u32 v) | ||
318 | { | ||
319 | return (v & 0x1) << 24; | ||
320 | } | ||
321 | static inline u32 pwr_falcon_imemd_r(u32 i) | ||
322 | { | ||
323 | return 0x0010a184 + i*16; | ||
324 | } | ||
325 | static inline u32 pwr_falcon_imemt_r(u32 i) | ||
326 | { | ||
327 | return 0x0010a188 + i*16; | ||
328 | } | ||
293 | static inline u32 pwr_falcon_bootvec_r(void) | 329 | static inline u32 pwr_falcon_bootvec_r(void) |
294 | { | 330 | { |
295 | return 0x0010a104; | 331 | return 0x0010a104; |