diff options
author | Randy Spurlock <rspurlock@nvidia.com> | 2014-05-05 19:37:54 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:09:22 -0400 |
commit | effa9dcfaa5220c6e59d421e1e3c90a97b86dc74 (patch) | |
tree | 048f9551b4f8ed4577dffb00f10cf19e87a9a614 /drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |
parent | acd6d02069b499bbaa83b7c5ba6a952e6a6fd476 (diff) |
video: tegra: host: gk20a: add class perf settings
Add a place to edit context-switched perf settings based upon
class. Disable tex-lock as the first of such for compute.
Bug 1409041
Change-Id: I5317a2a2e5f855661a1400b42f69211d16ae0c1d
Signed-off-by: Randy Spurlock <rspurlock@nvidia.com>
Reviewed-on: http://git-master/r/405908
(cherry picked from commit 250e149be35ecb8893dcef053ec44ffea86c302a)
Reviewed-on: http://git-master/r/407094
(cherry picked from commit 54337c08cbf6c2c6b5c929c1be24e87165d9d946)
Reviewed-on: http://git-master/r/408837
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index a28a1d0d..fad8d3a6 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |||
@@ -3190,4 +3190,56 @@ static inline u32 gr_gpc0_tpc0_l1c_dbg_cya15_en_f(void) | |||
3190 | { | 3190 | { |
3191 | return 0x8000000; | 3191 | return 0x8000000; |
3192 | } | 3192 | } |
3193 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_r(void) | ||
3194 | { | ||
3195 | return 0x00419ec8; | ||
3196 | } | ||
3197 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_m(void) | ||
3198 | { | ||
3199 | return 0x1 << 0; | ||
3200 | } | ||
3201 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_disable_f(void) | ||
3202 | { | ||
3203 | return 0x0; | ||
3204 | } | ||
3205 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_m(void) | ||
3206 | { | ||
3207 | return 0x1 << 1; | ||
3208 | } | ||
3209 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_disable_f(void) | ||
3210 | { | ||
3211 | return 0x0; | ||
3212 | } | ||
3213 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_m(void) | ||
3214 | { | ||
3215 | return 0x1 << 2; | ||
3216 | } | ||
3217 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_disable_f(void) | ||
3218 | { | ||
3219 | return 0x0; | ||
3220 | } | ||
3221 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_m(void) | ||
3222 | { | ||
3223 | return 0x1 << 3; | ||
3224 | } | ||
3225 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_disable_f(void) | ||
3226 | { | ||
3227 | return 0x0; | ||
3228 | } | ||
3229 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_m(void) | ||
3230 | { | ||
3231 | return 0xff << 4; | ||
3232 | } | ||
3233 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_disable_f(void) | ||
3234 | { | ||
3235 | return 0x0; | ||
3236 | } | ||
3237 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_m(void) | ||
3238 | { | ||
3239 | return 0x1 << 16; | ||
3240 | } | ||
3241 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_disable_f(void) | ||
3242 | { | ||
3243 | return 0x0; | ||
3244 | } | ||
3193 | #endif | 3245 | #endif |