diff options
author | sujeet baranwal <sbaranwal@nvidia.com> | 2015-03-02 18:36:22 -0500 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-04-04 21:58:04 -0400 |
commit | 895675e1d5790e2361b22edb50d702f7dd9a8edd (patch) | |
tree | dbe3586cec5351fd2c2eb13d91c258e663d73b08 /drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |
parent | cf0085ec231246748b34081d2786c29cedcbd706 (diff) |
gpu: nvgpu: Removal of regops from CUDA driver
The current CUDA drivers have been using the regops to
directly accessing the GPU registers from user space through
the dbg node. This is a security hole and needs to be avoided.
The patch alternatively implements the similar functionality
in the kernel and provide an ioctl for it.
Bug 200083334
Change-Id: Ic5ff5a215cbabe7a46837bc4e15efcceb0df0367
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/711758
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index 8fe75614..8a6c2f23 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |||
@@ -342,6 +342,30 @@ static inline u32 gr_activity_4_r(void) | |||
342 | { | 342 | { |
343 | return 0x00400390; | 343 | return 0x00400390; |
344 | } | 344 | } |
345 | static inline u32 gr_pri_gpc0_gcc_dbg_r(void) | ||
346 | { | ||
347 | return 0x00501000; | ||
348 | } | ||
349 | static inline u32 gr_pri_gpcs_gcc_dbg_r(void) | ||
350 | { | ||
351 | return 0x00419000; | ||
352 | } | ||
353 | static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) | ||
354 | { | ||
355 | return 0x1 << 1; | ||
356 | } | ||
357 | static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) | ||
358 | { | ||
359 | return 0x005046a4; | ||
360 | } | ||
361 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) | ||
362 | { | ||
363 | return 0x00419ea4; | ||
364 | } | ||
365 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) | ||
366 | { | ||
367 | return 0x1 << 0; | ||
368 | } | ||
345 | static inline u32 gr_pri_sked_activity_r(void) | 369 | static inline u32 gr_pri_sked_activity_r(void) |
346 | { | 370 | { |
347 | return 0x00407054; | 371 | return 0x00407054; |
@@ -2962,6 +2986,10 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) | |||
2962 | { | 2986 | { |
2963 | return 0x0050450c; | 2987 | return 0x0050450c; |
2964 | } | 2988 | } |
2989 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) | ||
2990 | { | ||
2991 | return (r >> 1) & 0x1; | ||
2992 | } | ||
2965 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) | 2993 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) |
2966 | { | 2994 | { |
2967 | return 0x2; | 2995 | return 0x2; |
@@ -3010,6 +3038,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) | |||
3010 | { | 3038 | { |
3011 | return 0x00000001; | 3039 | return 0x00000001; |
3012 | } | 3040 | } |
3041 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) | ||
3042 | { | ||
3043 | return 0x00000000; | ||
3044 | } | ||
3013 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) | 3045 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) |
3014 | { | 3046 | { |
3015 | return 0x80000000; | 3047 | return 0x80000000; |
@@ -3022,10 +3054,50 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) | |||
3022 | { | 3054 | { |
3023 | return 0x40000000; | 3055 | return 0x40000000; |
3024 | } | 3056 | } |
3057 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) | ||
3058 | { | ||
3059 | return (r >> 1) & 0x1; | ||
3060 | } | ||
3061 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) | ||
3062 | { | ||
3063 | return 0x0; | ||
3064 | } | ||
3065 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) | ||
3066 | { | ||
3067 | return (r >> 2) & 0x1; | ||
3068 | } | ||
3069 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) | ||
3070 | { | ||
3071 | return 0x0; | ||
3072 | } | ||
3073 | static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) | ||
3074 | { | ||
3075 | return 0x00504614; | ||
3076 | } | ||
3077 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) | ||
3078 | { | ||
3079 | return 0x00504624; | ||
3080 | } | ||
3081 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) | ||
3082 | { | ||
3083 | return 0x00504634; | ||
3084 | } | ||
3085 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void) | ||
3086 | { | ||
3087 | return 0x00000000; | ||
3088 | } | ||
3089 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_sm_disable_v(void) | ||
3090 | { | ||
3091 | return 0x00000000; | ||
3092 | } | ||
3025 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) | 3093 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) |
3026 | { | 3094 | { |
3027 | return 0x0050460c; | 3095 | return 0x0050460c; |
3028 | } | 3096 | } |
3097 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) | ||
3098 | { | ||
3099 | return (r >> 0) & 0x1; | ||
3100 | } | ||
3029 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) | 3101 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) |
3030 | { | 3102 | { |
3031 | return (r >> 4) & 0x1; | 3103 | return (r >> 4) & 0x1; |