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author | Vijayakumar <vsubbu@nvidia.com> | 2014-06-27 05:20:31 -0400 |
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committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:10:19 -0400 |
commit | 88c6d2fb21ad2f3f1be09c2014560aa22b27ba98 (patch) | |
tree | 9fdc0a988ca5697b1b97884e49d21a10762eb24d /drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |
parent | e0d7e42e8cc33cdb85543faadb2080fdee9a07ff (diff) |
gpu:nvgpu:fix powergate disabling order
ELPG has to disabled before we write to clock gating registers
If ELPG is engaged during clock gating register write it will
cause error in ELPG engine
Bug 200013495
Bug 200014542
Change-Id: I57d1c59fc9311686829d898faddc90149df4cb46
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/432117
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h')
0 files changed, 0 insertions, 0 deletions