diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2016-04-18 04:24:31 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-04-19 11:08:07 -0400 |
commit | 2b2f84219c4bd21be9a7abf34334ec6d443c6c38 (patch) | |
tree | 2405fcb040a91a35becda1c6df023e156251f7cd /drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |
parent | b63c4bced5b01e2aef477ecfca784848e2a2cd3a (diff) |
gpu: nvgpu: add accessors for global_esr values and sm_dbgr_control
Add gk20a/gm20b accessors for various global_esr values
and for sm_dbgr_control modes
Bug 200156699
Change-Id: If7fd8cd7567f8bcd1f645facf9553bdc0a153526
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1120333
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index ab2a975b..11cbe10c 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |||
@@ -938,10 +938,22 @@ static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) | |||
938 | { | 938 | { |
939 | return (v & 0x1) << 18; | 939 | return (v & 0x1) << 18; |
940 | } | 940 | } |
941 | static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) | ||
942 | { | ||
943 | return (v & 0xffff) << 0; | ||
944 | } | ||
941 | static inline u32 gr_fecs_host_int_clear_r(void) | 945 | static inline u32 gr_fecs_host_int_clear_r(void) |
942 | { | 946 | { |
943 | return 0x00409c20; | 947 | return 0x00409c20; |
944 | } | 948 | } |
949 | static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) | ||
950 | { | ||
951 | return (v & 0x1) << 1; | ||
952 | } | ||
953 | static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) | ||
954 | { | ||
955 | return 0x2; | ||
956 | } | ||
945 | static inline u32 gr_fecs_host_int_enable_r(void) | 957 | static inline u32 gr_fecs_host_int_enable_r(void) |
946 | { | 958 | { |
947 | return 0x00409c24; | 959 | return 0x00409c24; |
@@ -3102,6 +3114,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) | |||
3102 | { | 3114 | { |
3103 | return 0x0; | 3115 | return 0x0; |
3104 | } | 3116 | } |
3117 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void) | ||
3118 | { | ||
3119 | return 0x8; | ||
3120 | } | ||
3121 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void) | ||
3122 | { | ||
3123 | return 0x0; | ||
3124 | } | ||
3105 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) | 3125 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) |
3106 | { | 3126 | { |
3107 | return 0x40000000; | 3127 | return 0x40000000; |
@@ -3186,6 +3206,26 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f( | |||
3186 | { | 3206 | { |
3187 | return 0x40; | 3207 | return 0x40; |
3188 | } | 3208 | } |
3209 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) | ||
3210 | { | ||
3211 | return 0x1; | ||
3212 | } | ||
3213 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void) | ||
3214 | { | ||
3215 | return 0x2; | ||
3216 | } | ||
3217 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void) | ||
3218 | { | ||
3219 | return 0x4; | ||
3220 | } | ||
3221 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) | ||
3222 | { | ||
3223 | return 0x8; | ||
3224 | } | ||
3225 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void) | ||
3226 | { | ||
3227 | return 0x80000000; | ||
3228 | } | ||
3189 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) | 3229 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) |
3190 | { | 3230 | { |
3191 | return 0x00504650; | 3231 | return 0x00504650; |
@@ -3202,6 +3242,26 @@ static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f( | |||
3202 | { | 3242 | { |
3203 | return 0x40; | 3243 | return 0x40; |
3204 | } | 3244 | } |
3245 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) | ||
3246 | { | ||
3247 | return 0x1; | ||
3248 | } | ||
3249 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void) | ||
3250 | { | ||
3251 | return 0x2; | ||
3252 | } | ||
3253 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void) | ||
3254 | { | ||
3255 | return 0x4; | ||
3256 | } | ||
3257 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) | ||
3258 | { | ||
3259 | return 0x8; | ||
3260 | } | ||
3261 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void) | ||
3262 | { | ||
3263 | return 0x80000000; | ||
3264 | } | ||
3205 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) | 3265 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) |
3206 | { | 3266 | { |
3207 | return 0x00504224; | 3267 | return 0x00504224; |
@@ -3618,6 +3678,18 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) | |||
3618 | { | 3678 | { |
3619 | return 0x0; | 3679 | return 0x0; |
3620 | } | 3680 | } |
3681 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void) | ||
3682 | { | ||
3683 | return 0x1 << 3; | ||
3684 | } | ||
3685 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void) | ||
3686 | { | ||
3687 | return 0x8; | ||
3688 | } | ||
3689 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void) | ||
3690 | { | ||
3691 | return 0x0; | ||
3692 | } | ||
3621 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) | 3693 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) |
3622 | { | 3694 | { |
3623 | return 0x1 << 30; | 3695 | return 0x1 << 30; |