gpu: nvgpu: Per-chip interrupt processing

Move accesses to MC registers under HAL so that they can be
reimplemented per chip.

Do chip detection and HAL initialization only once.

Bug 1567274

Change-Id: I20bf2f439d267d284bfd536f1a1dfb5d5a2dce4c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590385

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
index 578b77bf..208c1ef0 100644
--- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
@@ -23,6 +23,7 @@
 #include "channel_gk20a.h"
 #include "gr_ctx_gk20a.h"
 #include "mm_gk20a.h"
+#include "mc_gk20a.h"
 #include "pmu_gk20a.h"
 #include "clk_gk20a.h"
 #include "regops_gk20a.h"
@@ -48,6 +49,7 @@ int gk20a_init_hal(struct gpu_ops *gops)
 {
         *gops = gk20a_ops;
         gops->privsecurity = 0;
+        gk20a_init_mc(gops);
         gk20a_init_ltc(gops);
         gk20a_init_gr_ops(gops);
         gk20a_init_fb(gops);