gpu: nvgpu: fix gm20b floorsweep API

Rewrite gr_gm20b_ctx_state_floorsweep() to include necessary
register writes for gm20b tpc floorsweeping.

This includes :
- update the loop to write gr_gpc0_tpc0_sm_cfg_r()
  and gr_gpc0_gpm_pd_sm_id_r()
- for gr_pd_num_tpc_per_gpc_r(i), we just need to write
  register with i = 0 and the value being written is tpc
  count in that gpc
- gr_fe_tpc_fs_r() needs to have logical list of TPCs after
  floorsweeping. Get this value from pes_tpc_mask.
- gr_cwd_gpc_tpc_id_tpc0_f() and gr_cwd_sm_id_tpc0_f()
  also refer to logical ids and hence no need to check
  tpc_fs_mask to configure these registers

Bug 1513685

Change-Id: I82dc36a223fbd21e814e58e4d67738d7c63f04a7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/601117
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

0 files changed, 0 insertions, 0 deletions