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| author | sujeet baranwal <sbaranwal@nvidia.com> | 2015-09-22 11:56:13 -0400 |
|---|---|---|
| committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-09-24 10:53:43 -0400 |
| commit | 6ceef08d52daabdf4911f28086e082b1dd2559f1 (patch) | |
| tree | abe98d12cf6d0b94a8f5af8d4d267d8eea7c7cc4 /drivers/gpu/nvgpu/gk20a/hal.h | |
| parent | 977acd877b68b51eb2f48a999077939378968c66 (diff) | |
gpu: nvgpu: Add CDE bits in FECS header
In case of CDE channel, T1 (Tex) unit needs to be promoted to 128B
aligned, otherwise causes a HW deadlock. Gpu driver makes changes in
FECS header which FECS uses to configure the T1 promotions to aligned
128B accesses.
Bug 200096226
Change-Id: Ic006b2c7035bbeabe1081aeed968a6c6d11f9995
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/802327
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/hal.h')
0 files changed, 0 insertions, 0 deletions