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| author | Seema Khowala <seemaj@nvidia.com> | 2016-09-15 17:37:31 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-10-14 11:11:20 -0400 |
| commit | 94efd53ed1c8202b4b46af41ec8ab580774f4974 (patch) | |
| tree | 8639358ff6be216c40755896b323ac9966107321 /drivers/gpu/nvgpu/gk20a/hal.c | |
| parent | 1029136eaa1c7c1cb9a9c8413af439fd741dc232 (diff) | |
gpu: nvgpu: fix zcull programming
There are eight tiles per map tile register and
depending on how many tpcs are present, there is
a chance that s/w will be accessing un-allocated
memory for reading tile values from temp buffers.
Bug 1735760
Change-Id: I5c0e09ec75099aaf6ad03dde964b9e93c2dc2408
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1221580
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/hal.c')
0 files changed, 0 insertions, 0 deletions