gpu: nvgpu: Full chip support for ctxsw

nvgpu changes needed to handle the newly added ctxsw lists
Fix regops support for ppc registers

Squashed from:
Change-Id: I08e6dec3bb2f7aa51de912c9d1c84a350ce07f72
Signed-off-by: neha <njoshi@nvidia.com>
Reviewed-on: http://git-master/r/1151010
(cherry picked from commit fd03ad9f09e66f78db88fb7ece448e26e0515821)

and:
Change-Id: I75a7f810ee0b613c22ac2cef2d936563d8067f97
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1158888
(cherry picked from commit f00a7fcc57fb937b800e46760087ff6f7637520c)

Bug 200180000
Bug 1771830

Reviewed-on: http://git-master/r/1164397
(cherry picked from commit 7028f051e4f37edeff90a9923f022cec6c645a8f)
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Change-Id: I796ddf93ef37170843a4a6b44190cd6780d25852
Reviewed-on: http://git-master/r/1183588
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
GVS: Gerrit_Virtual_Submit

1 files changed, 29 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h
index a7656d38..88521555 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h
@@ -69,6 +69,35 @@ static inline u32 pri_get_gpc_num(struct gk20a *g, u32 addr)
         }
         return 0;
 }
+
+/*
+ * PPC pri addressing
+ */
+static inline bool pri_is_ppc_addr_shared(struct gk20a *g, u32 addr)
+{
+        u32 ppc_in_gpc_shared_base = nvgpu_get_litter_value(g,
+                                                GPU_LIT_PPC_IN_GPC_SHARED_BASE);
+        u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g,
+                                                GPU_LIT_PPC_IN_GPC_STRIDE);
+
+        return ((addr >= ppc_in_gpc_shared_base) &&
+                (addr < (ppc_in_gpc_shared_base + ppc_in_gpc_stride)));
+}
+
+static inline bool pri_is_ppc_addr(struct gk20a *g, u32 addr)
+{
+        u32 ppc_in_gpc_base = nvgpu_get_litter_value(g,
+                                                GPU_LIT_PPC_IN_GPC_BASE);
+        u32 num_pes_per_gpc = nvgpu_get_litter_value(g,
+                                                GPU_LIT_NUM_PES_PER_GPC);
+        u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g,
+                                                GPU_LIT_PPC_IN_GPC_STRIDE);
+
+        return ((addr >= ppc_in_gpc_base) &&
+                (addr < ppc_in_gpc_base + num_pes_per_gpc * ppc_in_gpc_stride))
+                || pri_is_ppc_addr_shared(g, addr);
+}
+
 /*
  * TPC pri addressing
  */