gpu: nvgpu: hwpm broadcast register support

Add support for hwpm broadcast registers (ltc and lts)

In gr_gk20a_find_priv_offset_in_buffer, replace "Unknown address type" error
with informational message: gr_gk20a_exec_ctx_ops calls
gk20a_get_ctx_buffer_offsets and if that fails,
calls gr_gk20a_get_pm_ctx_buffer_offsets; HWPM registers will fail the first
call, so an error or warning is overkill.

Bug 1648200

Change-Id: I197b82579e9894652add4ff254418f818981415a
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1131365
(cherry picked from commit 9f30a92c5d87f6dadd34cc37396a6b10e3a72751)
Reviewed-on: http://git-master/r/1133628
(cherry picked from commit 7eb7cfd998852ba7f7c4c40d3db286f66e83ab3a)
Reviewed-on: http://git-master/r/1127749
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 17 insertions, 6 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h
index 248fa291..62e276de 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h
@@ -1,7 +1,7 @@
 /*
  * GK20A Graphics Context Pri Register Addressing
  *
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -167,12 +167,21 @@ static inline u32 pri_ppc_addr(struct gk20a *g, u32 addr, u32 gpc, u32 ppc)
                 ppc_in_gpc_base + (ppc * ppc_in_gpc_stride) + addr;
 }
 
+/*
+ * LTC pri addressing
+ */
+static inline bool pri_is_ltc_addr(u32 addr)
+{
+        return ((addr >= ltc_pltcg_base_v()) && (addr < ltc_pltcg_extent_v()));
+}
+
 enum ctxsw_addr_type {
-        CTXSW_ADDR_TYPE_SYS = 0,
-        CTXSW_ADDR_TYPE_GPC = 1,
-        CTXSW_ADDR_TYPE_TPC = 2,
-        CTXSW_ADDR_TYPE_BE  = 3,
-        CTXSW_ADDR_TYPE_PPC = 4
+        CTXSW_ADDR_TYPE_SYS  = 0,
+        CTXSW_ADDR_TYPE_GPC  = 1,
+        CTXSW_ADDR_TYPE_TPC  = 2,
+        CTXSW_ADDR_TYPE_BE   = 3,
+        CTXSW_ADDR_TYPE_PPC  = 4,
+        CTXSW_ADDR_TYPE_LTCS = 5
 };
 
 #define PRI_BROADCAST_FLAGS_NONE  0
@@ -180,5 +189,7 @@ enum ctxsw_addr_type {
 #define PRI_BROADCAST_FLAGS_TPC   BIT(1)
 #define PRI_BROADCAST_FLAGS_BE    BIT(2)
 #define PRI_BROADCAST_FLAGS_PPC   BIT(3)
+#define PRI_BROADCAST_FLAGS_LTCS  BIT(4)
+#define PRI_BROADCAST_FLAGS_LTSS  BIT(5)
 
 #endif /* GR_PRI_GK20A_H */