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author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-08-13 15:58:18 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-16 13:14:40 -0400 |
commit | 974d541623929fa2622d27d5d338a5b63596794b (patch) | |
tree | f47a540bf07efd7f6cda68f49d3675c2462d731a /drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h | |
parent | 1e7f229e5d92078f772d4f81893b23504cd847a8 (diff) |
gpu: nvgpu: Move ltc HAL to common
Move implementation of ltc HAL to common/ltc.
JIRA NVGPU-956
Change-Id: Id78d74e8612d7dacfb8d322d491abecd798e42b5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1798461
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h index af390833..32a30d78 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h | |||
@@ -29,8 +29,6 @@ | |||
29 | * of the context state store for gr/compute contexts. | 29 | * of the context state store for gr/compute contexts. |
30 | */ | 30 | */ |
31 | 31 | ||
32 | #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h> | ||
33 | |||
34 | /* | 32 | /* |
35 | * GPC pri addressing | 33 | * GPC pri addressing |
36 | */ | 34 | */ |
@@ -227,14 +225,6 @@ static inline u32 pri_ppc_addr(struct gk20a *g, u32 addr, u32 gpc, u32 ppc) | |||
227 | ppc_in_gpc_base + (ppc * ppc_in_gpc_stride) + addr; | 225 | ppc_in_gpc_base + (ppc * ppc_in_gpc_stride) + addr; |
228 | } | 226 | } |
229 | 227 | ||
230 | /* | ||
231 | * LTC pri addressing | ||
232 | */ | ||
233 | static inline bool pri_is_ltc_addr(u32 addr) | ||
234 | { | ||
235 | return ((addr >= ltc_pltcg_base_v()) && (addr < ltc_pltcg_extent_v())); | ||
236 | } | ||
237 | |||
238 | enum ctxsw_addr_type { | 228 | enum ctxsw_addr_type { |
239 | CTXSW_ADDR_TYPE_SYS = 0, | 229 | CTXSW_ADDR_TYPE_SYS = 0, |
240 | CTXSW_ADDR_TYPE_GPC = 1, | 230 | CTXSW_ADDR_TYPE_GPC = 1, |