diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-01-17 15:39:13 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-23 01:20:15 -0500 |
commit | f3f14cdff53f4b936e2505d44aad6e3bca143056 (patch) | |
tree | 8d6438132b8ca429758d18142c5f569f60f2bc35 /drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |
parent | 193a2ed38ca51d898ac811820ab86237c84e18eb (diff) |
gpu: nvgpu: Fold T19x code back to main code paths
Lots of code paths were split to T19x specific code paths and structs
due to split repository. Now that repositories are merged, fold all of
them back to main code paths and structs and remove the T19x specific
Kconfig flag.
Change-Id: Id0d17a5f0610fc0b49f51ab6664e716dc8b222b6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640606
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 6cc15c94..d1c32c03 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -24,10 +24,6 @@ | |||
24 | #ifndef GR_GK20A_H | 24 | #ifndef GR_GK20A_H |
25 | #define GR_GK20A_H | 25 | #define GR_GK20A_H |
26 | 26 | ||
27 | #ifdef CONFIG_TEGRA_19x_GPU | ||
28 | #include "gr_t19x.h" | ||
29 | #endif | ||
30 | |||
31 | #include "gr_ctx_gk20a.h" | 27 | #include "gr_ctx_gk20a.h" |
32 | #include "mm_gk20a.h" | 28 | #include "mm_gk20a.h" |
33 | 29 | ||
@@ -199,6 +195,12 @@ struct zbc_depth_table { | |||
199 | u32 ref_cnt; | 195 | u32 ref_cnt; |
200 | }; | 196 | }; |
201 | 197 | ||
198 | struct zbc_s_table { | ||
199 | u32 stencil; | ||
200 | u32 format; | ||
201 | u32 ref_cnt; | ||
202 | }; | ||
203 | |||
202 | struct zbc_entry { | 204 | struct zbc_entry { |
203 | u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE]; | 205 | u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE]; |
204 | u32 color_l2[GK20A_ZBC_COLOR_VALUE_SIZE]; | 206 | u32 color_l2[GK20A_ZBC_COLOR_VALUE_SIZE]; |
@@ -393,20 +395,14 @@ struct gr_gk20a { | |||
393 | struct nvgpu_mutex zbc_lock; | 395 | struct nvgpu_mutex zbc_lock; |
394 | struct zbc_color_table zbc_col_tbl[GK20A_ZBC_TABLE_SIZE]; | 396 | struct zbc_color_table zbc_col_tbl[GK20A_ZBC_TABLE_SIZE]; |
395 | struct zbc_depth_table zbc_dep_tbl[GK20A_ZBC_TABLE_SIZE]; | 397 | struct zbc_depth_table zbc_dep_tbl[GK20A_ZBC_TABLE_SIZE]; |
396 | #ifdef CONFIG_TEGRA_19x_GPU | ||
397 | struct zbc_s_table zbc_s_tbl[GK20A_ZBC_TABLE_SIZE]; | 398 | struct zbc_s_table zbc_s_tbl[GK20A_ZBC_TABLE_SIZE]; |
398 | #endif | ||
399 | s32 max_default_color_index; | 399 | s32 max_default_color_index; |
400 | s32 max_default_depth_index; | 400 | s32 max_default_depth_index; |
401 | #ifdef CONFIG_TEGRA_19x_GPU | ||
402 | s32 max_default_s_index; | 401 | s32 max_default_s_index; |
403 | #endif | ||
404 | 402 | ||
405 | u32 max_used_color_index; | 403 | u32 max_used_color_index; |
406 | u32 max_used_depth_index; | 404 | u32 max_used_depth_index; |
407 | #ifdef CONFIG_TEGRA_19x_GPU | ||
408 | u32 max_used_s_index; | 405 | u32 max_used_s_index; |
409 | #endif | ||
410 | 406 | ||
411 | #define GR_CHANNEL_MAP_TLB_SIZE 2 /* must of power of 2 */ | 407 | #define GR_CHANNEL_MAP_TLB_SIZE 2 /* must of power of 2 */ |
412 | struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE]; | 408 | struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE]; |