diff options
author | Alex Waterman <alexw@nvidia.com> | 2017-03-21 15:55:35 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-06 21:14:53 -0400 |
commit | c9665079d7b12f22a847c62587724b4ee120ca6e (patch) | |
tree | 7882bd08193db4c34b3b8ad7df7013339da2fba1 /drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |
parent | b69020bff5dfa69cad926c9374cdbe9a62509ffd (diff) |
gpu: nvgpu: rename mem_desc to nvgpu_mem
Renaming was done with the following command:
$ find -type f | \
xargs sed -i 's/struct mem_desc/struct nvgpu_mem/g'
Also rename mem_desc.[ch] to nvgpu_mem.[ch].
JIRA NVGPU-12
Change-Id: I69395758c22a56aa01e3dffbcded70a729bf559a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1325547
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 3a4d5e04..e05eeb3d 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -205,7 +205,7 @@ struct gr_gk20a_isr_data { | |||
205 | 205 | ||
206 | struct gr_ctx_buffer_desc { | 206 | struct gr_ctx_buffer_desc { |
207 | void (*destroy)(struct gk20a *, struct gr_ctx_buffer_desc *); | 207 | void (*destroy)(struct gk20a *, struct gr_ctx_buffer_desc *); |
208 | struct mem_desc mem; | 208 | struct nvgpu_mem mem; |
209 | void *priv; | 209 | void *priv; |
210 | }; | 210 | }; |
211 | 211 | ||
@@ -321,8 +321,8 @@ struct gr_gk20a { | |||
321 | 321 | ||
322 | struct gr_ctx_buffer_desc global_ctx_buffer[NR_GLOBAL_CTX_BUF]; | 322 | struct gr_ctx_buffer_desc global_ctx_buffer[NR_GLOBAL_CTX_BUF]; |
323 | 323 | ||
324 | struct mem_desc mmu_wr_mem; | 324 | struct nvgpu_mem mmu_wr_mem; |
325 | struct mem_desc mmu_rd_mem; | 325 | struct nvgpu_mem mmu_rd_mem; |
326 | 326 | ||
327 | u8 *map_tiles; | 327 | u8 *map_tiles; |
328 | u32 map_tile_count; | 328 | u32 map_tile_count; |
@@ -385,7 +385,7 @@ struct gr_gk20a { | |||
385 | void gk20a_fecs_dump_falcon_stats(struct gk20a *g); | 385 | void gk20a_fecs_dump_falcon_stats(struct gk20a *g); |
386 | 386 | ||
387 | struct gr_ctx_desc { | 387 | struct gr_ctx_desc { |
388 | struct mem_desc mem; | 388 | struct nvgpu_mem mem; |
389 | 389 | ||
390 | u32 graphics_preempt_mode; | 390 | u32 graphics_preempt_mode; |
391 | u32 compute_preempt_mode; | 391 | u32 compute_preempt_mode; |
@@ -399,7 +399,7 @@ struct gr_ctx_desc { | |||
399 | }; | 399 | }; |
400 | 400 | ||
401 | struct ctx_header_desc { | 401 | struct ctx_header_desc { |
402 | struct mem_desc mem; | 402 | struct nvgpu_mem mem; |
403 | }; | 403 | }; |
404 | 404 | ||
405 | struct gk20a_ctxsw_ucode_segment { | 405 | struct gk20a_ctxsw_ucode_segment { |
@@ -441,8 +441,8 @@ struct gk20a_ctxsw_ucode_segments { | |||
441 | 441 | ||
442 | struct gk20a_ctxsw_ucode_info { | 442 | struct gk20a_ctxsw_ucode_info { |
443 | u64 *p_va; | 443 | u64 *p_va; |
444 | struct mem_desc inst_blk_desc; | 444 | struct nvgpu_mem inst_blk_desc; |
445 | struct mem_desc surface_desc; | 445 | struct nvgpu_mem surface_desc; |
446 | struct gk20a_ctxsw_ucode_segments fecs; | 446 | struct gk20a_ctxsw_ucode_segments fecs; |
447 | struct gk20a_ctxsw_ucode_segments gpccs; | 447 | struct gk20a_ctxsw_ucode_segments gpccs; |
448 | }; | 448 | }; |
@@ -526,7 +526,7 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr); | |||
526 | /* pmu */ | 526 | /* pmu */ |
527 | int gr_gk20a_fecs_get_reglist_img_size(struct gk20a *g, u32 *size); | 527 | int gr_gk20a_fecs_get_reglist_img_size(struct gk20a *g, u32 *size); |
528 | int gr_gk20a_fecs_set_reglist_bind_inst(struct gk20a *g, | 528 | int gr_gk20a_fecs_set_reglist_bind_inst(struct gk20a *g, |
529 | struct mem_desc *inst_block); | 529 | struct nvgpu_mem *inst_block); |
530 | int gr_gk20a_fecs_set_reglist_virtual_addr(struct gk20a *g, u64 pmu_va); | 530 | int gr_gk20a_fecs_set_reglist_virtual_addr(struct gk20a *g, u64 pmu_va); |
531 | 531 | ||
532 | void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine); | 532 | void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine); |
@@ -717,10 +717,10 @@ void gr_gk20a_init_sm_id_table(struct gk20a *g); | |||
717 | int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va); | 717 | int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va); |
718 | 718 | ||
719 | void gr_gk20a_write_zcull_ptr(struct gk20a *g, | 719 | void gr_gk20a_write_zcull_ptr(struct gk20a *g, |
720 | struct mem_desc *mem, u64 gpu_va); | 720 | struct nvgpu_mem *mem, u64 gpu_va); |
721 | 721 | ||
722 | void gr_gk20a_write_pm_ptr(struct gk20a *g, | 722 | void gr_gk20a_write_pm_ptr(struct gk20a *g, |
723 | struct mem_desc *mem, u64 gpu_va); | 723 | struct nvgpu_mem *mem, u64 gpu_va); |
724 | 724 | ||
725 | 725 | ||
726 | static inline const char *gr_gk20a_graphics_preempt_mode_name(u32 graphics_preempt_mode) | 726 | static inline const char *gr_gk20a_graphics_preempt_mode_name(u32 graphics_preempt_mode) |