diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2017-11-10 08:02:37 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-11-14 07:58:39 -0500 |
commit | 90aeab9dee07a63e4bac6d92646dfd80e65d2edd (patch) | |
tree | a175a1724590dc14c599db9c23f04d79a8f3ac79 /drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |
parent | fd2cac59f3491cb5b4f5d1f3fc97df94734bd682 (diff) |
gpu: nvgpu: define preemption modes in common code
We use linux specific graphics/compute preemption modes defined in uapi header
(and of below form) in all over common code
NVGPU_GRAPHICS_PREEMPTION_MODE_*
NVGPU_COMPUTE_PREEMPTION_MODE_*
Since common code should be independent of linux specific code, define new modes
of the form in common code and used them everywhere
NVGPU_PREEMPTION_MODE_GRAPHICS_*
NVGPU_PREEMPTION_MODE_COMPUTE_*
Add required parser functions to convert both the modes into each other
For linux IOCTL NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE, we need to convert
linux specific modes into common modes first before passing them to common code
And to pass gpu characteristics to user space we need to first convert common
modes into linux specific modes and then pass them to user space
Jira NVGPU-392
Change-Id: I8c62c6859bdc1baa5b44eb31c7020e42d2462c8c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1596930
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index b437838f..3377df5d 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -61,6 +61,13 @@ | |||
61 | (PAGE_SIZE/(PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY * sizeof(u32))) | 61 | (PAGE_SIZE/(PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY * sizeof(u32))) |
62 | #define PATCH_CTX_ENTRIES_FROM_SIZE(size) (size/sizeof(u32)) | 62 | #define PATCH_CTX_ENTRIES_FROM_SIZE(size) (size/sizeof(u32)) |
63 | 63 | ||
64 | #define NVGPU_PREEMPTION_MODE_GRAPHICS_WFI (1 << 0) | ||
65 | #define NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP (1 << 1) | ||
66 | |||
67 | #define NVGPU_PREEMPTION_MODE_COMPUTE_WFI (1 << 0) | ||
68 | #define NVGPU_PREEMPTION_MODE_COMPUTE_CTA (1 << 1) | ||
69 | #define NVGPU_PREEMPTION_MODE_COMPUTE_CILP (1 << 2) | ||
70 | |||
64 | struct channel_gk20a; | 71 | struct channel_gk20a; |
65 | struct nvgpu_warpstate; | 72 | struct nvgpu_warpstate; |
66 | 73 | ||
@@ -403,7 +410,6 @@ struct gr_gk20a { | |||
403 | bool sw_ready; | 410 | bool sw_ready; |
404 | bool skip_ucode_init; | 411 | bool skip_ucode_init; |
405 | 412 | ||
406 | struct nvgpu_preemption_modes_rec preemption_mode_rec; | ||
407 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | 413 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC |
408 | struct gr_t18x t18x; | 414 | struct gr_t18x t18x; |
409 | #endif | 415 | #endif |