diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2014-05-14 08:22:49 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:10:05 -0400 |
commit | 6b33379c55a8368ce9e5ed1381f9aeeebe383dfe (patch) | |
tree | 625ae2366c0b21d9c4b18255f691f506debfcbfb /drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |
parent | cd13ee4aafcdb0206078e9e41aca53107235bbed (diff) |
gpu: nvgpu: Rewrite PMU boot-up sequence
Rewrite PMU boot sequence as a state machine. At PMU power-up send
initial messages, and reset state machine. At each reply from PMU,
do the next stage of PMU boot and set state.
As now PMU and FECS boot are independent, we need to ensure engine
idle before saving ZBC.
Change-Id: I1ea747ab794ef08f1784eeabfdae7655d585ff21
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/410205
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 9e0883d6..05c27ffd 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -204,7 +204,9 @@ struct gr_gk20a { | |||
204 | #define GR_NETLIST_STATIC_A 'A' | 204 | #define GR_NETLIST_STATIC_A 'A' |
205 | int netlist; | 205 | int netlist; |
206 | 206 | ||
207 | wait_queue_head_t init_wq; | ||
207 | int initialized; | 208 | int initialized; |
209 | |||
208 | u32 num_fbps; | 210 | u32 num_fbps; |
209 | 211 | ||
210 | u32 comptags_per_cacheline; | 212 | u32 comptags_per_cacheline; |
@@ -313,9 +315,11 @@ struct gk20a_ctxsw_bootloader_desc { | |||
313 | }; | 315 | }; |
314 | 316 | ||
315 | struct gpu_ops; | 317 | struct gpu_ops; |
316 | void gk20a_init_gr(struct gpu_ops *gops); | 318 | void gk20a_init_gr(struct gk20a *g); |
319 | void gk20a_init_gr_ops(struct gpu_ops *gops); | ||
317 | int gk20a_init_gr_support(struct gk20a *g); | 320 | int gk20a_init_gr_support(struct gk20a *g); |
318 | int gk20a_gr_reset(struct gk20a *g); | 321 | int gk20a_gr_reset(struct gk20a *g); |
322 | void gk20a_gr_wait_initialized(struct gk20a *g); | ||
319 | 323 | ||
320 | int gk20a_init_gr_channel(struct channel_gk20a *ch_gk20a); | 324 | int gk20a_init_gr_channel(struct channel_gk20a *ch_gk20a); |
321 | 325 | ||
@@ -356,14 +360,17 @@ int gr_gk20a_fecs_set_reglist_virtual_addr(struct gk20a *g, u64 pmu_va); | |||
356 | void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine); | 360 | void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine); |
357 | void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine); | 361 | void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine); |
358 | 362 | ||
363 | void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries); | ||
364 | |||
359 | /* sm */ | 365 | /* sm */ |
360 | bool gk20a_gr_sm_debugger_attached(struct gk20a *g); | 366 | bool gk20a_gr_sm_debugger_attached(struct gk20a *g); |
361 | 367 | ||
362 | #define gr_gk20a_elpg_protected_call(g, func) \ | 368 | #define gr_gk20a_elpg_protected_call(g, func) \ |
363 | ({ \ | 369 | ({ \ |
364 | int err; \ | 370 | int err = 0; \ |
365 | if (support_gk20a_pmu()) \ | 371 | if (support_gk20a_pmu()) \ |
366 | gk20a_pmu_disable_elpg(g); \ | 372 | err = gk20a_pmu_disable_elpg(g); \ |
373 | if (err) return err; \ | ||
367 | err = func; \ | 374 | err = func; \ |
368 | if (support_gk20a_pmu()) \ | 375 | if (support_gk20a_pmu()) \ |
369 | gk20a_pmu_enable_elpg(g); \ | 376 | gk20a_pmu_enable_elpg(g); \ |