diff options
author | Nicolin Chen <nicolinc@nvidia.com> | 2018-08-13 23:22:56 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-22 20:33:42 -0400 |
commit | 52305f0514d29e7fb2cb5e2154188e09faa3fe94 (patch) | |
tree | f5b50db358366692188e008ee2303dc5135e65ea /drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |
parent | d5473e225decc74f0d6bb015d06365dad15828d0 (diff) |
gpu: nvgpu: Reduce structure padding waste
The gk20a_init_fifo_setup_sw_common() function allocates memory of
schannel_gk20a and tsg_gk20a tructures for all 512 channels:
Size Caller Module Pages Type
749568 __nvgpu_vzalloc+0x28/0x78 [nvgpu] pages=182 vmalloc
602112 __nvgpu_vzalloc+0x28/0x78 [nvgpu] pages=146 vmalloc
This change just simply reorgnizes the member defines in those two
structures to reduce padding waste. After this change:
Size Caller Module Pages Type
733184 __nvgpu_vzalloc+0x28/0x78 [nvgpu] pages=178 vmalloc
585728 __nvgpu_vzalloc+0x28/0x78 [nvgpu] pages=142 vmalloc
In summary, it saves 8 pages in 32KB memory.
Bug 2327574
Bug 2284925
Change-Id: I06693e0fef516a145b48dd3a05d756c0feaf3ba5
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803358
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index a60f6f12..3fc7e55f 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -453,7 +453,6 @@ struct nvgpu_gr_ctx { | |||
453 | 453 | ||
454 | u32 graphics_preempt_mode; | 454 | u32 graphics_preempt_mode; |
455 | u32 compute_preempt_mode; | 455 | u32 compute_preempt_mode; |
456 | bool boosted_ctx; | ||
457 | 456 | ||
458 | struct nvgpu_mem preempt_ctxsw_buffer; | 457 | struct nvgpu_mem preempt_ctxsw_buffer; |
459 | struct nvgpu_mem spill_ctxsw_buffer; | 458 | struct nvgpu_mem spill_ctxsw_buffer; |
@@ -462,11 +461,12 @@ struct nvgpu_gr_ctx { | |||
462 | u32 ctx_id; | 461 | u32 ctx_id; |
463 | bool ctx_id_valid; | 462 | bool ctx_id_valid; |
464 | bool cilp_preempt_pending; | 463 | bool cilp_preempt_pending; |
464 | bool boosted_ctx; | ||
465 | bool golden_img_loaded; | ||
465 | 466 | ||
466 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | 467 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION |
467 | u64 virt_ctx; | 468 | u64 virt_ctx; |
468 | #endif | 469 | #endif |
469 | bool golden_img_loaded; | ||
470 | 470 | ||
471 | struct patch_desc patch_ctx; | 471 | struct patch_desc patch_ctx; |
472 | struct zcull_ctx_desc zcull_ctx; | 472 | struct zcull_ctx_desc zcull_ctx; |