gpu: nvgpu: add sm lock_down gr ops

Add lock_down_sm and wait_for_sm_lock_down gr ops
Required to support multiple SM and t19x SM register
address changes

JIRA GPUT19X-75

Change-Id: I529babde51d9b2143fe3740a4f67c582b7eb404b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514042
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 4 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 8230ba72..77db5cf6 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -622,9 +622,6 @@ void gk20a_gr_suspend_single_sm(struct gk20a *g,
 void gk20a_gr_suspend_all_sms(struct gk20a *g,
                 u32 global_esr_mask, bool check_errors);
 u32 gr_gk20a_get_tpc_count(struct gr_gk20a *gr, u32 gpc_index);
-int gk20a_gr_lock_down_sm(struct gk20a *g,
-                                 u32 gpc, u32 tpc, u32 global_esr_mask,
-                                 bool check_errors);
 int gr_gk20a_set_sm_debug_mode(struct gk20a *g,
         struct channel_gk20a *ch, u64 sms, bool enable);
 bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch);
@@ -681,7 +678,10 @@ static inline void gr_gk20a_free_cyclestats_snapshot_data(struct gk20a *g)
 
 int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
                 struct gr_gk20a_isr_data *isr_data);
-int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc,
+int gk20a_gr_lock_down_sm(struct gk20a *g,
+                         u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask,
+                         bool check_errors);
+int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
                 u32 global_esr_mask, bool check_errors);
 void gk20a_gr_clear_sm_hww(struct gk20a *g,
                 u32 gpc, u32 tpc, u32 global_esr);