gpu: nvgpu: ZBC update without idle

Do ZBC updates without forcing engine idle first.

Bug 1698013

Change-Id: I99218c8cfd02be05dace2003b8d91921765f7ca9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/829145

1 files changed, 2 insertions, 72 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 0cb18665..090f95a5 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -3456,42 +3456,6 @@ int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
         return 0;
 }
 
-void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries)
-{
-        struct fifo_gk20a *f = &g->fifo;
-        struct fifo_engine_info_gk20a *gr_info =
-                f->engine_info + ENGINE_GR_GK20A;
-        unsigned long end_jiffies = jiffies +
-                msecs_to_jiffies(gk20a_get_gr_idle_timeout(g));
-        u32 ret;
-
-        ret = gk20a_fifo_disable_engine_activity(g, gr_info, true);
-        if (ret) {
-                gk20a_err(dev_from_gk20a(g),
-                        "failed to disable gr engine activity\n");
-                return;
-        }
-
-        ret = g->ops.gr.wait_empty(g, end_jiffies, GR_IDLE_CHECK_DEFAULT);
-        if (ret) {
-                gk20a_err(dev_from_gk20a(g),
-                        "failed to idle graphics\n");
-                goto clean_up;
-        }
-
-        /* update zbc */
-        gk20a_pmu_save_zbc(g, entries);
-
-clean_up:
-        ret = gk20a_fifo_enable_engine_activity(g, gr_info);
-        if (ret) {
-                gk20a_err(dev_from_gk20a(g),
-                        "failed to enable gr engine activity\n");
-        }
-
-        return;
-}
-
 int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
                      struct zbc_entry *zbc_val)
 {
@@ -3584,7 +3548,7 @@ int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
                 /* update zbc for elpg only when new entry is added */
                 entries = max(gr->max_used_color_index,
                                         gr->max_used_depth_index);
-                gr_gk20a_pmu_save_zbc(g, entries);
+                gk20a_pmu_save_zbc(g, entries);
         }
 
 err_mutex:
@@ -3739,47 +3703,13 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr)
         return 0;
 }
 
-static int _gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
-                        struct zbc_entry *zbc_val)
-{
-        struct fifo_gk20a *f = &g->fifo;
-        struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A;
-        unsigned long end_jiffies;
-        int ret;
-
-        ret = gk20a_fifo_disable_engine_activity(g, gr_info, true);
-        if (ret) {
-                gk20a_err(dev_from_gk20a(g),
-                        "failed to disable gr engine activity\n");
-                return ret;
-        }
-
-        end_jiffies = jiffies + msecs_to_jiffies(gk20a_get_gr_idle_timeout(g));
-        ret = g->ops.gr.wait_empty(g, end_jiffies, GR_IDLE_CHECK_DEFAULT);
-        if (ret) {
-                gk20a_err(dev_from_gk20a(g),
-                        "failed to idle graphics\n");
-                goto clean_up;
-        }
-
-        ret = gr_gk20a_add_zbc(g, gr, zbc_val);
-
-clean_up:
-        if (gk20a_fifo_enable_engine_activity(g, gr_info)) {
-                gk20a_err(dev_from_gk20a(g),
-                        "failed to enable gr engine activity\n");
-        }
-
-        return ret;
-}
-
 int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
                         struct zbc_entry *zbc_val)
 {
         gk20a_dbg_fn("");
 
         return gr_gk20a_elpg_protected_call(g,
-                _gk20a_gr_zbc_set_table(g, gr, zbc_val));
+                gr_gk20a_add_zbc(g, gr, zbc_val));
 }
 
 void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine)