diff options
author | Vaibhav Kachore <vkachore@nvidia.com> | 2018-07-06 05:40:03 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-07-10 21:13:43 -0400 |
commit | e14fdcd8f1f4125da697433b1744b1e4e4f15b09 (patch) | |
tree | f48ff794ef77e977ccba397f5abf14f5ae7b185b /drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |
parent | 4cd59404a2d4ab1c31605d96cff848dd4e93c3b4 (diff) |
gpu: nvgpu: enable HWPM Mode-E context switch
- Write new pm mode to context buffer header. Ucode use
this mode to enable mode-e context switch. This is Mode-B
context switch of PMs with Mode-E streamout on one context.
If this mode is set, Ucode makes sure that Mode-E pipe
(perfmons, routers, pma) is idle before it context switches PMs.
- This allows us to collect counters in a secure way
(i.e. on context basis) with stream out.
Bug 2106999
Change-Id: I5a7435f09d1bf053ca428e538b0a57f3a175ac37
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1760366
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 46 |
1 files changed, 35 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 7a65f353..3f49fbf7 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -1684,14 +1684,14 @@ out: | |||
1684 | int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, | 1684 | int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, |
1685 | struct channel_gk20a *c, | 1685 | struct channel_gk20a *c, |
1686 | u64 gpu_va, | 1686 | u64 gpu_va, |
1687 | bool enable_hwpm_ctxsw) | 1687 | u32 mode) |
1688 | { | 1688 | { |
1689 | struct tsg_gk20a *tsg; | 1689 | struct tsg_gk20a *tsg; |
1690 | struct nvgpu_mem *gr_mem = NULL; | 1690 | struct nvgpu_mem *gr_mem = NULL; |
1691 | struct nvgpu_gr_ctx *gr_ctx; | 1691 | struct nvgpu_gr_ctx *gr_ctx; |
1692 | struct pm_ctx_desc *pm_ctx; | 1692 | struct pm_ctx_desc *pm_ctx; |
1693 | u32 data; | 1693 | u32 data; |
1694 | u64 virt_addr; | 1694 | u64 virt_addr = 0; |
1695 | struct ctx_header_desc *ctx = &c->ctx_header; | 1695 | struct ctx_header_desc *ctx = &c->ctx_header; |
1696 | struct nvgpu_mem *ctxheader = &ctx->mem; | 1696 | struct nvgpu_mem *ctxheader = &ctx->mem; |
1697 | int ret; | 1697 | int ret; |
@@ -1710,12 +1710,31 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, | |||
1710 | return -EFAULT; | 1710 | return -EFAULT; |
1711 | } | 1711 | } |
1712 | 1712 | ||
1713 | if (enable_hwpm_ctxsw) { | 1713 | if ((mode == NVGPU_DBG_HWPM_CTXSW_MODE_STREAM_OUT_CTXSW) && |
1714 | if (pm_ctx->pm_mode == ctxsw_prog_main_image_pm_mode_ctxsw_f()) | 1714 | (!g->ops.gr.get_hw_accessor_stream_out_mode)) { |
1715 | nvgpu_err(g, "Mode-E hwpm context switch mode is not supported"); | ||
1716 | return -EINVAL; | ||
1717 | } | ||
1718 | |||
1719 | switch (mode) { | ||
1720 | case NVGPU_DBG_HWPM_CTXSW_MODE_CTXSW: | ||
1721 | if (pm_ctx->pm_mode == ctxsw_prog_main_image_pm_mode_ctxsw_f()) { | ||
1715 | return 0; | 1722 | return 0; |
1716 | } else { | 1723 | } |
1717 | if (pm_ctx->pm_mode == ctxsw_prog_main_image_pm_mode_no_ctxsw_f()) | 1724 | break; |
1725 | case NVGPU_DBG_HWPM_CTXSW_MODE_NO_CTXSW: | ||
1726 | if (pm_ctx->pm_mode == ctxsw_prog_main_image_pm_mode_no_ctxsw_f()) { | ||
1727 | return 0; | ||
1728 | } | ||
1729 | break; | ||
1730 | case NVGPU_DBG_HWPM_CTXSW_MODE_STREAM_OUT_CTXSW: | ||
1731 | if (pm_ctx->pm_mode == g->ops.gr.get_hw_accessor_stream_out_mode()) { | ||
1718 | return 0; | 1732 | return 0; |
1733 | } | ||
1734 | break; | ||
1735 | default: | ||
1736 | nvgpu_err(g, "invalid hwpm context switch mode"); | ||
1737 | return -EINVAL; | ||
1719 | } | 1738 | } |
1720 | 1739 | ||
1721 | ret = gk20a_disable_channel_tsg(g, c); | 1740 | ret = gk20a_disable_channel_tsg(g, c); |
@@ -1735,7 +1754,7 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, | |||
1735 | Flush and invalidate before cpu update. */ | 1754 | Flush and invalidate before cpu update. */ |
1736 | g->ops.mm.l2_flush(g, true); | 1755 | g->ops.mm.l2_flush(g, true); |
1737 | 1756 | ||
1738 | if (enable_hwpm_ctxsw) { | 1757 | if (mode != NVGPU_DBG_HWPM_CTXSW_MODE_NO_CTXSW) { |
1739 | /* Allocate buffer if necessary */ | 1758 | /* Allocate buffer if necessary */ |
1740 | if (pm_ctx->mem.gpu_va == 0) { | 1759 | if (pm_ctx->mem.gpu_va == 0) { |
1741 | ret = nvgpu_dma_alloc_sys(g, | 1760 | ret = nvgpu_dma_alloc_sys(g, |
@@ -1768,11 +1787,16 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, | |||
1768 | data = nvgpu_mem_rd(g, gr_mem, ctxsw_prog_main_image_pm_o()); | 1787 | data = nvgpu_mem_rd(g, gr_mem, ctxsw_prog_main_image_pm_o()); |
1769 | data = data & ~ctxsw_prog_main_image_pm_mode_m(); | 1788 | data = data & ~ctxsw_prog_main_image_pm_mode_m(); |
1770 | 1789 | ||
1771 | if (enable_hwpm_ctxsw) { | 1790 | switch (mode) { |
1791 | case NVGPU_DBG_HWPM_CTXSW_MODE_CTXSW: | ||
1772 | pm_ctx->pm_mode = ctxsw_prog_main_image_pm_mode_ctxsw_f(); | 1792 | pm_ctx->pm_mode = ctxsw_prog_main_image_pm_mode_ctxsw_f(); |
1773 | |||
1774 | virt_addr = pm_ctx->mem.gpu_va; | 1793 | virt_addr = pm_ctx->mem.gpu_va; |
1775 | } else { | 1794 | break; |
1795 | case NVGPU_DBG_HWPM_CTXSW_MODE_STREAM_OUT_CTXSW: | ||
1796 | pm_ctx->pm_mode = g->ops.gr.get_hw_accessor_stream_out_mode(); | ||
1797 | virt_addr = pm_ctx->mem.gpu_va; | ||
1798 | break; | ||
1799 | case NVGPU_DBG_HWPM_CTXSW_MODE_NO_CTXSW: | ||
1776 | pm_ctx->pm_mode = ctxsw_prog_main_image_pm_mode_no_ctxsw_f(); | 1800 | pm_ctx->pm_mode = ctxsw_prog_main_image_pm_mode_no_ctxsw_f(); |
1777 | virt_addr = 0; | 1801 | virt_addr = 0; |
1778 | } | 1802 | } |
@@ -1892,7 +1916,7 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g, | |||
1892 | * for PM context switching, including mode and possibly a pointer to | 1916 | * for PM context switching, including mode and possibly a pointer to |
1893 | * the PM backing store. | 1917 | * the PM backing store. |
1894 | */ | 1918 | */ |
1895 | if (gr_ctx->pm_ctx.pm_mode == ctxsw_prog_main_image_pm_mode_ctxsw_f()) { | 1919 | if (gr_ctx->pm_ctx.pm_mode != ctxsw_prog_main_image_pm_mode_no_ctxsw_f()) { |
1896 | if (gr_ctx->pm_ctx.mem.gpu_va == 0) { | 1920 | if (gr_ctx->pm_ctx.mem.gpu_va == 0) { |
1897 | nvgpu_err(g, | 1921 | nvgpu_err(g, |
1898 | "context switched pm with no pm buffer!"); | 1922 | "context switched pm with no pm buffer!"); |