summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
diff options
context:
space:
mode:
authorKonsta Holtta <kholtta@nvidia.com>2016-06-17 08:51:02 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-07-05 02:10:59 -0400
commite12c5c8594c429357427130389da632284d79bcc (patch)
tree453043237ef411370a02ec03c6857b63480c019b /drivers/gpu/nvgpu/gk20a/gr_gk20a.c
parentcd5a1dc315abd0a7db4136ee0e6b0c03f0882937 (diff)
gpu: nvgpu: initial support for vidmem apertures
add gk20a_aperture_mask() for memory target selection now that buffers can actually be allocated from vidmem, and use it in all cases that have a mem_desc available. Jira DNVGPU-76 Change-Id: I4353cdc6e1e79488f0875581cfaf2a5cfb8c976a Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1169306 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c66
1 files changed, 28 insertions, 38 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 9790af05..bdc65cab 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -674,11 +674,24 @@ void gr_gk20a_ctx_patch_write(struct gk20a *g,
674 } 674 }
675} 675}
676 676
677static u32 fecs_current_ctx_data(struct gk20a *g, struct mem_desc *inst_block)
678{
679 u32 ptr = u64_lo32(gk20a_mm_inst_block_addr(g, inst_block)
680 >> ram_in_base_shift_v());
681 u32 aperture = gk20a_aperture_mask(g, inst_block,
682 gr_fecs_current_ctx_target_sys_mem_ncoh_f(),
683 gr_fecs_current_ctx_target_vid_mem_f());
684
685 return gr_fecs_current_ctx_ptr_f(ptr) | aperture |
686 gr_fecs_current_ctx_valid_f(1);
687}
688
677static int gr_gk20a_fecs_ctx_bind_channel(struct gk20a *g, 689static int gr_gk20a_fecs_ctx_bind_channel(struct gk20a *g,
678 struct channel_gk20a *c) 690 struct channel_gk20a *c)
679{ 691{
680 u32 inst_base_ptr = u64_lo32(gk20a_mm_inst_block_addr(g, &c->inst_block) 692 u32 inst_base_ptr = u64_lo32(gk20a_mm_inst_block_addr(g, &c->inst_block)
681 >> ram_in_base_shift_v()); 693 >> ram_in_base_shift_v());
694 u32 data = fecs_current_ctx_data(g, &c->inst_block);
682 u32 ret; 695 u32 ret;
683 696
684 gk20a_dbg_info("bind channel %d inst ptr 0x%08x", 697 gk20a_dbg_info("bind channel %d inst ptr 0x%08x",
@@ -687,11 +700,7 @@ static int gr_gk20a_fecs_ctx_bind_channel(struct gk20a *g,
687 ret = gr_gk20a_submit_fecs_method_op(g, 700 ret = gr_gk20a_submit_fecs_method_op(g,
688 (struct fecs_method_op_gk20a) { 701 (struct fecs_method_op_gk20a) {
689 .method.addr = gr_fecs_method_push_adr_bind_pointer_v(), 702 .method.addr = gr_fecs_method_push_adr_bind_pointer_v(),
690 .method.data = (gr_fecs_current_ctx_ptr_f(inst_base_ptr) | 703 .method.data = data,
691 (g->mm.vidmem_is_vidmem ?
692 gr_fecs_current_ctx_target_sys_mem_ncoh_f() :
693 gr_fecs_current_ctx_target_vid_mem_f()) |
694 gr_fecs_current_ctx_valid_f(1)),
695 .mailbox = { .id = 0, .data = 0, 704 .mailbox = { .id = 0, .data = 0,
696 .clr = 0x30, 705 .clr = 0x30,
697 .ret = NULL, 706 .ret = NULL,
@@ -1392,21 +1401,12 @@ static int gr_gk20a_fecs_ctx_image_save(struct channel_gk20a *c, u32 save_type)
1392 struct gk20a *g = c->g; 1401 struct gk20a *g = c->g;
1393 int ret; 1402 int ret;
1394 1403
1395 u32 inst_base_ptr =
1396 u64_lo32(gk20a_mm_inst_block_addr(g, &c->inst_block)
1397 >> ram_in_base_shift_v());
1398
1399
1400 gk20a_dbg_fn(""); 1404 gk20a_dbg_fn("");
1401 1405
1402 ret = gr_gk20a_submit_fecs_method_op(g, 1406 ret = gr_gk20a_submit_fecs_method_op(g,
1403 (struct fecs_method_op_gk20a) { 1407 (struct fecs_method_op_gk20a) {
1404 .method.addr = save_type, 1408 .method.addr = save_type,
1405 .method.data = (gr_fecs_current_ctx_ptr_f(inst_base_ptr) | 1409 .method.data = fecs_current_ctx_data(g, &c->inst_block),
1406 (g->mm.vidmem_is_vidmem ?
1407 gr_fecs_current_ctx_target_sys_mem_ncoh_f() :
1408 gr_fecs_current_ctx_target_vid_mem_f()) |
1409 gr_fecs_current_ctx_valid_f(1)),
1410 .mailbox = {.id = 0, .data = 0, .clr = 3, .ret = NULL, 1410 .mailbox = {.id = 0, .data = 0, .clr = 3, .ret = NULL,
1411 .ok = 1, .fail = 2, 1411 .ok = 1, .fail = 2,
1412 }, 1412 },
@@ -1987,18 +1987,11 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g,
1987 gk20a_mem_end(g, mem); 1987 gk20a_mem_end(g, mem);
1988 1988
1989 if (tegra_platform_is_linsim()) { 1989 if (tegra_platform_is_linsim()) {
1990 u32 inst_base_ptr = 1990 u32 mdata = fecs_current_ctx_data(g, &c->inst_block);
1991 u64_lo32(gk20a_mm_inst_block_addr(g, &c->inst_block)
1992 >> ram_in_base_shift_v());
1993 1991
1994 ret = gr_gk20a_submit_fecs_method_op(g, 1992 ret = gr_gk20a_submit_fecs_method_op(g,
1995 (struct fecs_method_op_gk20a) { 1993 (struct fecs_method_op_gk20a) {
1996 .method.data = 1994 .method.data = mdata,
1997 (gr_fecs_current_ctx_ptr_f(inst_base_ptr) |
1998 (g->mm.vidmem_is_vidmem ?
1999 gr_fecs_current_ctx_target_sys_mem_ncoh_f() :
2000 gr_fecs_current_ctx_target_vid_mem_f()) |
2001 gr_fecs_current_ctx_valid_f(1)),
2002 .method.addr = 1995 .method.addr =
2003 gr_fecs_method_push_adr_restore_golden_v(), 1996 gr_fecs_method_push_adr_restore_golden_v(),
2004 .mailbox = { 1997 .mailbox = {
@@ -4507,8 +4500,8 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
4507 addr >>= fb_mmu_debug_wr_addr_alignment_v(); 4500 addr >>= fb_mmu_debug_wr_addr_alignment_v();
4508 4501
4509 gk20a_writel(g, fb_mmu_debug_wr_r(), 4502 gk20a_writel(g, fb_mmu_debug_wr_r(),
4510 (g->mm.vidmem_is_vidmem ? 4503 gk20a_aperture_mask(g, &gr->mmu_wr_mem,
4511 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f() : 4504 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(),
4512 fb_mmu_debug_wr_aperture_vid_mem_f()) | 4505 fb_mmu_debug_wr_aperture_vid_mem_f()) |
4513 fb_mmu_debug_wr_vol_false_f() | 4506 fb_mmu_debug_wr_vol_false_f() |
4514 fb_mmu_debug_wr_addr_f(addr)); 4507 fb_mmu_debug_wr_addr_f(addr));
@@ -4517,8 +4510,8 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
4517 addr >>= fb_mmu_debug_rd_addr_alignment_v(); 4510 addr >>= fb_mmu_debug_rd_addr_alignment_v();
4518 4511
4519 gk20a_writel(g, fb_mmu_debug_rd_r(), 4512 gk20a_writel(g, fb_mmu_debug_rd_r(),
4520 (g->mm.vidmem_is_vidmem ? 4513 gk20a_aperture_mask(g, &gr->mmu_rd_mem,
4521 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f() : 4514 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(),
4522 fb_mmu_debug_rd_aperture_vid_mem_f()) | 4515 fb_mmu_debug_rd_aperture_vid_mem_f()) |
4523 fb_mmu_debug_rd_vol_false_f() | 4516 fb_mmu_debug_rd_vol_false_f() |
4524 fb_mmu_debug_rd_addr_f(addr)); 4517 fb_mmu_debug_rd_addr_f(addr));
@@ -4966,8 +4959,7 @@ static int gk20a_init_gr_bind_fecs_elpg(struct gk20a *g)
4966 } 4959 }
4967 4960
4968 4961
4969 err = gr_gk20a_fecs_set_reglist_bind_inst(g, 4962 err = gr_gk20a_fecs_set_reglist_bind_inst(g, &mm->pmu.inst_block);
4970 gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block));
4971 if (err) { 4963 if (err) {
4972 gk20a_err(dev_from_gk20a(g), 4964 gk20a_err(dev_from_gk20a(g),
4973 "fail to bind pmu inst to gr"); 4965 "fail to bind pmu inst to gr");
@@ -5245,8 +5237,7 @@ int gk20a_gr_reset(struct gk20a *g)
5245 return err; 5237 return err;
5246 } 5238 }
5247 5239
5248 err = gr_gk20a_fecs_set_reglist_bind_inst(g, 5240 err = gr_gk20a_fecs_set_reglist_bind_inst(g, &g->mm.pmu.inst_block);
5249 gk20a_mm_inst_block_addr(g, &g->mm.pmu.inst_block));
5250 if (err) { 5241 if (err) {
5251 gk20a_err(dev_from_gk20a(g), 5242 gk20a_err(dev_from_gk20a(g),
5252 "fail to bind pmu inst to gr"); 5243 "fail to bind pmu inst to gr");
@@ -6346,16 +6337,15 @@ int gr_gk20a_fecs_get_reglist_img_size(struct gk20a *g, u32 *size)
6346 .mailbox.fail = 0}, false); 6337 .mailbox.fail = 0}, false);
6347} 6338}
6348 6339
6349int gr_gk20a_fecs_set_reglist_bind_inst(struct gk20a *g, phys_addr_t addr) 6340int gr_gk20a_fecs_set_reglist_bind_inst(struct gk20a *g,
6341 struct mem_desc *inst_block)
6350{ 6342{
6343 u32 data = fecs_current_ctx_data(g, inst_block);
6344
6351 return gr_gk20a_submit_fecs_method_op(g, 6345 return gr_gk20a_submit_fecs_method_op(g,
6352 (struct fecs_method_op_gk20a){ 6346 (struct fecs_method_op_gk20a){
6353 .mailbox.id = 4, 6347 .mailbox.id = 4,
6354 .mailbox.data = (gr_fecs_current_ctx_ptr_f(addr >> 12) | 6348 .mailbox.data = data,
6355 gr_fecs_current_ctx_valid_f(1) |
6356 (g->mm.vidmem_is_vidmem ?
6357 gr_fecs_current_ctx_target_sys_mem_ncoh_f() :
6358 gr_fecs_current_ctx_target_vid_mem_f())),
6359 .mailbox.clr = ~0, 6349 .mailbox.clr = ~0,
6360 .method.data = 1, 6350 .method.data = 1,
6361 .method.addr = gr_fecs_method_push_adr_set_reglist_bind_instance_v(), 6351 .method.addr = gr_fecs_method_push_adr_set_reglist_bind_instance_v(),