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authorPeter Daifuku <pdaifuku@nvidia.com>2017-10-27 18:46:53 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-11-03 02:27:12 -0400
commitde399ccb0019513a5f9e8f2bcadb02486f99bc80 (patch)
treef3bc9e054f501fd4c9cf8c20b614ae160c8a6dd1 /drivers/gpu/nvgpu/gk20a/gr_gk20a.c
parent566223689538531783a86091f052f70a6ebdef29 (diff)
gpu: nvgpu: fix patch buf count update for vidmem
gr_gk20a_ctx_patch_write_begin() updates the patch buffer data_count when the associated graphics context memory buffer has been CPU-mapped; it was doing so by looking for a non-null cpu_va. However, if the graphics context has been allocated from vidmem, cpu_va is always 0, so we can't tell if nvgpu_mem_begin() was called for the context buffer or not. Instead: - add a cpu_accessible flag to the nvgpu_mem struct and set it in nvgpu_mem_begin() - return the value of that flag in nvgpu_mem_cpu_accessible() - gr_gk20a_ctx_patch_write_begin() now calls this new function instead of checking cpu_va. Bug 2012077 JIRA ESRM-74 Change-Id: I8401699f30b4ae7154111721c25c7ec3ff95d329 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1587293 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 2a20c2d9..06fb5497 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -682,7 +682,7 @@ int gr_gk20a_ctx_patch_write_begin(struct gk20a *g,
682 if (err) 682 if (err)
683 return err; 683 return err;
684 684
685 if (ch_ctx->gr_ctx->mem.cpu_va) { 685 if (nvgpu_mem_cpu_accessible(&ch_ctx->gr_ctx->mem)) {
686 /* reset patch count if ucode has already processed it */ 686 /* reset patch count if ucode has already processed it */
687 ch_ctx->patch_ctx.data_count = nvgpu_mem_rd(g, 687 ch_ctx->patch_ctx.data_count = nvgpu_mem_rd(g,
688 &ch_ctx->gr_ctx->mem, 688 &ch_ctx->gr_ctx->mem,
@@ -699,7 +699,7 @@ void gr_gk20a_ctx_patch_write_end(struct gk20a *g,
699 nvgpu_mem_end(g, &ch_ctx->patch_ctx.mem); 699 nvgpu_mem_end(g, &ch_ctx->patch_ctx.mem);
700 700
701 /* Write context count to context image if it is mapped */ 701 /* Write context count to context image if it is mapped */
702 if (ch_ctx->gr_ctx->mem.cpu_va) { 702 if (nvgpu_mem_cpu_accessible(&ch_ctx->gr_ctx->mem)) {
703 nvgpu_mem_wr(g, &ch_ctx->gr_ctx->mem, 703 nvgpu_mem_wr(g, &ch_ctx->gr_ctx->mem,
704 ctxsw_prog_main_image_patch_count_o(), 704 ctxsw_prog_main_image_patch_count_o(),
705 ch_ctx->patch_ctx.data_count); 705 ch_ctx->patch_ctx.data_count);