gpu: nvgpu: add hal op for gr set error notifier

The vserver variant for gr set error notifier needs different
functionality to send interrupt to VM. Add HAL operation to
allow overriding vserver usecase.

Jira VQRM-2982

Change-Id: Ia445a27112bb6c5587dbb81100a9dafe5875b338
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1657830
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 9 insertions, 9 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 6abc7d41..b37ae8cd 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5113,7 +5113,7 @@ int gk20a_gr_reset(struct gk20a *g)
         return err;
 }
 
-static void gk20a_gr_set_error_notifier(struct gk20a *g,
+void gk20a_gr_set_error_notifier(struct gk20a *g,
                   struct gr_gk20a_isr_data *isr_data, u32 error_notifier)
 {
         struct fifo_gk20a *f = &g->fifo;
@@ -5146,7 +5146,7 @@ static int gk20a_gr_handle_semaphore_timeout_pending(struct gk20a *g,
                   struct gr_gk20a_isr_data *isr_data)
 {
         gk20a_dbg_fn("");
-        gk20a_gr_set_error_notifier(g, isr_data,
+        g->ops.gr.set_error_notifier(g, isr_data,
                          NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT);
         nvgpu_err(g,
                    "gr semaphore timeout");
@@ -5157,7 +5157,7 @@ static int gk20a_gr_intr_illegal_notify_pending(struct gk20a *g,
                   struct gr_gk20a_isr_data *isr_data)
 {
         gk20a_dbg_fn("");
-        gk20a_gr_set_error_notifier(g, isr_data,
+        g->ops.gr.set_error_notifier(g, isr_data,
                          NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY);
         /* This is an unrecoverable error, reset is needed */
         nvgpu_err(g,
@@ -5172,7 +5172,7 @@ static int gk20a_gr_handle_illegal_method(struct gk20a *g,
                         isr_data->class_num, isr_data->offset,
                         isr_data->data_lo);
         if (ret) {
-                gk20a_gr_set_error_notifier(g, isr_data,
+                g->ops.gr.set_error_notifier(g, isr_data,
                          NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY);
                 nvgpu_err(g, "invalid method class 0x%08x"
                         ", offset 0x%08x address 0x%08x",
@@ -5185,7 +5185,7 @@ static int gk20a_gr_handle_illegal_class(struct gk20a *g,
                                           struct gr_gk20a_isr_data *isr_data)
 {
         gk20a_dbg_fn("");
-        gk20a_gr_set_error_notifier(g, isr_data,
+        g->ops.gr.set_error_notifier(g, isr_data,
                          NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
         nvgpu_err(g,
                    "invalid class 0x%08x, offset 0x%08x",
@@ -5203,7 +5203,7 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
                 return 0;
 
         if (gr_fecs_intr & gr_fecs_host_int_status_umimp_firmware_method_f(1)) {
-                gk20a_gr_set_error_notifier(g, isr_data,
+                g->ops.gr.set_error_notifier(g, isr_data,
                          NVGPU_ERR_NOTIFIER_FECS_ERR_UNIMP_FIRMWARE_METHOD);
                 nvgpu_err(g,
                           "firmware method error 0x%08x for offset 0x%04x",
@@ -5229,7 +5229,7 @@ static int gk20a_gr_handle_class_error(struct gk20a *g,
 
         gr_class_error =
                 gr_class_error_code_v(gk20a_readl(g, gr_class_error_r()));
-        gk20a_gr_set_error_notifier(g, isr_data,
+        g->ops.gr.set_error_notifier(g, isr_data,
                          NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
         nvgpu_err(g, "class error 0x%08x, offset 0x%08x,"
                 "sub channel 0x%08x mme generated %d,"
@@ -5258,7 +5258,7 @@ static int gk20a_gr_handle_firmware_method(struct gk20a *g,
 {
         gk20a_dbg_fn("");
 
-        gk20a_gr_set_error_notifier(g, isr_data,
+        g->ops.gr.set_error_notifier(g, isr_data,
                          NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
         nvgpu_err(g,
                    "firmware method 0x%08x, offset 0x%08x for channel %u",
@@ -6064,7 +6064,7 @@ int gk20a_gr_isr(struct gk20a *g)
 
                 if (need_reset) {
                         nvgpu_err(g, "set gr exception notifier");
-                        gk20a_gr_set_error_notifier(g, &isr_data,
+                        g->ops.gr.set_error_notifier(g, &isr_data,
                                          NVGPU_ERR_NOTIFIER_GR_EXCEPTION);
                 }
         }