gpu: nvgpu: enhance class error debug info

Updated gk20a_gr_handle_class_error with
sub channel info, mme related info.

Also printing the correct method info from
isr_data->offset by left shifting it by 2.

Generated following hw definitions for gk20a/gm20b/gp10b/gp106
to dump relevant data in gk20a_gr_handle_class_error:
gr_trapped_addr_mme_generated_v
gr_trapped_addr_datahigh_v
gr_trapped_addr_priv_v
gr_trapped_data_lo_r
gr_trapped_data_mme_r
gr_trapped_data_mme_pc_v

Bug 2003671

Change-Id: I02e15ef16d7498b6a7dc2af547a14e84d570e8a7
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1574061
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 18 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 241e6525..d6732453 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5202,11 +5202,24 @@ static int gk20a_gr_handle_class_error(struct gk20a *g,
                 gr_class_error_code_v(gk20a_readl(g, gr_class_error_r()));
         gk20a_gr_set_error_notifier(g, isr_data,
                          NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY);
-        nvgpu_err(g,
-                   "class error 0x%08x, offset 0x%08x,"
-                        " unhandled intr 0x%08x for channel %u",
-                   isr_data->class_num, isr_data->offset,
-                   gr_class_error, isr_data->chid);
+        nvgpu_err(g, "class error 0x%08x, offset 0x%08x,"
+                "sub channel 0x%08x mme generated %d,"
+                " mme pc 0x%08xdata high %d priv status %d"
+                " unhandled intr 0x%08x for channel %u",
+                isr_data->class_num, (isr_data->offset << 2),
+                gr_trapped_addr_subch_v(isr_data->addr),
+                gr_trapped_addr_mme_generated_v(isr_data->addr),
+                gr_trapped_data_mme_pc_v(
+                        gk20a_readl(g, gr_trapped_data_mme_r())),
+                gr_trapped_addr_datahigh_v(isr_data->addr),
+                gr_trapped_addr_priv_v(isr_data->addr),
+                gr_class_error, isr_data->chid);
+
+        nvgpu_err(g, "trapped data low 0x%08x",
+                gk20a_readl(g, gr_trapped_data_lo_r()));
+        if (gr_trapped_addr_datahigh_v(isr_data->addr))
+                nvgpu_err(g, "trapped data high 0x%08x",
+                gk20a_readl(g, gr_trapped_data_hi_r()));
 
         return -EINVAL;
 }